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Home Digital Electronics Flip-Flops Comments

  • Question
  • The output of a gated S-R flip-flop changes only if the:


  • Options
  • A. flip-flop is set
  • B. control input data has changed
  • C. flip-flop is reset
  • D. input data has no change

  • Correct Answer
  • control input data has changed 


  • Flip-Flops problems


    Search Results


    • 1. A correct output is achieved from a master-slave J-K flip-flop only if its inputs are stable while the:

    • Options
    • A. clock is LOW
    • B. slave is transferring
    • C. flip-flop is reset
    • D. clock is HIGH
    • Discuss
    • 2. A push-button switch is used to input data to a register. The output of the register is erratic. What could be causing the problem?

    • Options
    • A. The power supply is probably noisy.
    • B. The switch contacts are bouncing.
    • C. The socket contacts on the register IC are corroded.
    • D. The register IC is intermittent and failure is imminent.
    • Discuss
    • 3. What is one disadvantage of an S-R flip-flop?

    • Options
    • A. It has no enable input.
    • B. It has an invalid state.
    • C. It has no clock input.
    • D. It has only a single output.
    • Discuss
    • 4. Which of the following is correct for a gated D flip-flop?

    • Options
    • A. The output toggles if one of the inputs is held HIGH.
    • B. Only one of the inputs can be HIGH at a time.
    • C. The output complement follows the input when enabled.
    • D. Q output follows the input D when the enable is HIGH.
    • Discuss
    • 5. If an input is activated by a signal transition, it is ________.

    • Options
    • A. edge-triggered
    • B. toggle triggered
    • C. clock triggered
    • D. noise triggered
    • Discuss
    • 6. The toggle condition in a master-slave J-K flip-flop means that Q and will switch to their ________ state(s) at the ________.

    • Options
    • A. opposite, active clock edge
    • B. inverted, positive clock edge
    • C. quiescent, negative clock edge
    • D. reset, synchronous clock edge
    • Discuss
    • 7. Which is not an Altera primitive port identifier?

    • Options
    • A. clk
    • B. ena
    • C. clr
    • D. prn
    • Discuss
    • 8. What is the difference between a 7490 and a 7492?

    • Options
    • A. 7490 is a MOD-12, 7492 is a MOD-10
    • B. 7490 is a MOD-12, 7492 is a MOD-16
    • C. 7490 is a MOD-16, 7492 is a MOD-10
    • D. 7490 is a MOD-10, 7492 is a MOD-12
    • Discuss
    • 9. List the state of each output pin of a 7447 if RBI = 0, LT = 1, A0 = 1, A1 = 0, A2 = 0, and A3 = 1.

    • Options
    • A. RBO = 0, a = 0, b = 0, c = 0, d = 1, e = 1, f = 0, g = 0
    • B. RBO = 1, a = 0, b = 0, c = 0, d = 1, e = 1, f = 0, g = 0
    • C. RBO = 0, a = 0, b = 0, c = 0, d = 0, e = 1, f = 0, g = 0
    • D. RBO = 1, a = 0, b = 0, c = 0, d = 0, e = 1, f = 0, g = 0
    • Discuss
    • 10. The hexadecimal equivalent of 15,536 is ________.

    • Options
    • A. 3CB0
    • B. 3C66
    • C. 63C0
    • D. 6300
    • Discuss


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