Discussion
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- Question
What is one disadvantage of an S-R flip-flop?
Options- A. It has no enable input.
- B. It has an invalid state.
- C. It has no clock input.
- D. It has only a single output.
- Correct Answer
- It has an invalid state.
- 1. Which of the following is correct for a gated D flip-flop?
Options- A. The output toggles if one of the inputs is held HIGH.
- B. Only one of the inputs can be HIGH at a time.
- C. The output complement follows the input when enabled.
- D. Q output follows the input D when the enable is HIGH. Discuss
- 2. If an input is activated by a signal transition, it is ________.
Options- A. edge-triggered
- B. toggle triggered
- C. clock triggered
- D. noise triggered Discuss
- 3. Determine the output frequency for a frequency division circuit that contains 12 flip-flops with an input clock frequency of 20.48 MHz.
Options- A. 10.24 kHz
- B. 5 kHz
- C. 30.24 kHz
- D. 15 kHz Discuss
- 4. One example of the use of an S-R flip-flop is as a(n):
Options- A. racer
- B. astable oscillator
- C. binary storage register
- D. transition pulse generator Discuss
- 5. In VHDL, how many inputs will a primitive JK flip-flop have?
Options- A. 2
- B. 3
- C. 4
- D. 5 Discuss
- 6. A push-button switch is used to input data to a register. The output of the register is erratic. What could be causing the problem?
Options- A. The power supply is probably noisy.
- B. The switch contacts are bouncing.
- C. The socket contacts on the register IC are corroded.
- D. The register IC is intermittent and failure is imminent. Discuss
- 7. A correct output is achieved from a master-slave J-K flip-flop only if its inputs are stable while the:
Options- A. clock is LOW
- B. slave is transferring
- C. flip-flop is reset
- D. clock is HIGH Discuss
- 8. The output of a gated S-R flip-flop changes only if the:
Options- A. flip-flop is set
- B. control input data has changed
- C. flip-flop is reset
- D. input data has no change Discuss
- 9. The toggle condition in a master-slave J-K flip-flop means that Q and
will switch to their ________ state(s) at the ________.
Options- A. opposite, active clock edge
- B. inverted, positive clock edge
- C. quiescent, negative clock edge
- D. reset, synchronous clock edge Discuss
- 10. Which is not an Altera primitive port identifier?
Options- A. clk
- B. ena
- C. clr
- D. prn Discuss
Flip-Flops problems
Search Results
Correct Answer: Q output follows the input D when the enable is HIGH.
Correct Answer: edge-triggered
Correct Answer: 5 kHz
Correct Answer: binary storage register
Correct Answer: 5
Correct Answer: The switch contacts are bouncing.
Correct Answer: clock is HIGH
Correct Answer: control input data has changed
Correct Answer: opposite, active clock edge
Correct Answer: clr
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