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Home ‣ Digital Electronics ‣ Flip-Flops Comments
  • Question

  • A positive edge-triggered J-K flip-flop is used to produce a two-phase clock. However, when the circuit is operated it produces erratic results. Close examination with a scope reveals the presence of glitches. What causes the glitches, and how might the problem be corrected?


  • Options
  • A. The PRESET and CLEAR terminals may have been left floating; they should be properly terminated if not being used.
  • B. The problem is caused by a race condition between the J and K inputs; an inverter should be inserted in one of the terminals to correct the problem.
  • C. A race condition exists between the Q and Q outputs to the AND gate; the AND gate should be replaced with a NAND gate.
  • D. A race condition exists between the clock and the outputs of the flip-flop feeding the AND gate; replace the flip-flop with a negative edge-triggered J-K Flip-Flop.

  • Correct Answer
  • A race condition exists between the clock and the outputs of the flip-flop feeding the AND gate; replace the flip-flop with a negative edge-triggered J-K Flip-Flop. 

    • Flip-Flops problems

    Search Results

    • 1. How many flip-flops are required to produce a divide-by-128 device?

    • Options
    • A. 1
    • B. 4
    • C. 6
    • D. 7
      • Discuss
    • 2. Which statement BEST describes the operation of a negative-edge-triggered D flip-flop?

    • Options
    • A. The logic level at the D input is transferred to Q on NGT of CLK.
    • B. The Q output is ALWAYS identical to the CLK input if the D input is HIGH.
    • C. The Q output is ALWAYS identical to the D input when CLK = PGT.
    • D. The Q output is ALWAYS identical to the D input.
      • Discuss
    • 3. How is a J-K flip-flop made to toggle?

    • Options
    • A. J = 0, K = 0
    • B. J = 1, K = 0
    • C. J = 0, K = 1
    • D. J = 1, K = 1
      • Discuss
    • 4. If both inputs of an S-R flip-flop are low, what will happen when the clock goes HIGH?

    • Options
    • A. An invalid state will exist.
    • B. No change will occur in the output.
    • C. The output will toggle.
    • D. The output will reset.
      • Discuss
    • 5. What is the significance of the J and K terminals on the J-K flip-flop?

    • Options
    • A. There is no known significance in their designations.
    • B. The J represents "jump," which is how the Q output reacts whenever the clock goes high and the J input is also HIGH.
    • C. The letters were chosen in honor of Jack Kilby, the inventory of the integrated circuit.
    • D. All of the other letters of the alphabet are already in use.
      • Discuss
    • 6. For an S-R flip-flop to be set or reset, the respective input must be:

    • Options
    • A. installed with steering diodes
    • B. in parallel with a limiting resistor
    • C. LOW
    • D. HIGH
      • Discuss
    • 7. A 555 operating as a monostable multivibrator has an R1 of 220 kΩ. Determine C1 for a pulse width of 4 ms.

    • Options
    • A. 0.017 µF
    • B. 17 pF
    • C. 170 pF
    • D. 1,700 µF
      • Discuss
    • 8. Which is not a real advantage of HDL?

    • Options
    • A. Using higher levels of abstraction
    • B. Tailoring components to exactly fit the needs of the project
    • C. The use of graphical tools
    • D. Using higher levels of abstraction and tailoring components to exactly fit the needs of the project
      • Discuss
    • 9. A gated S-R latch and its associated waveforms are shown below. What, if anything, is wrong and what could be causing the problem?


    • Options
    • A. The output is always low; the circuit is defective.
    • B. The Q output should be the complement of the output; the S and R terminals are reversed.
    • C. The Q should be following the R input; the R input is defective.
    • D. There is nothing wrong with the circuit.
      • Discuss
    • 10. A 555 operating as a monostable multivibrator has an R1 of 1 MΩ. Determine C1 for a pulse width of 2 s.

    • Options
    • A. 1.8 µF
    • B. 18 F
    • C. 18 pF
    • D. 18 nF
      • Discuss

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