DRAM controllers — essential roles In a typical dynamic RAM (DRAM) subsystem, which two core functions are handled by the DRAM controller?

Introduction / Context:
Dynamic RAM relies on a controller to manage row/column addressing and periodic refresh. Without these, the capacitive cells would quickly lose charge and the memory would be unusable. Knowing the controller’s duties clarifies why DRAM differs from SRAM in interface complexity.

Given Data / Assumptions:

• DRAM uses multiplexed address buses: row address (RAS) and column address (CAS).
• Stored charge leaks with time; all rows must be refreshed periodically.
• “Data selection” is typically handled by bus interfaces or MUX/DEMUX logic outside the DRAM core protocol.

Concept / Approach:
The controller breaks a full address into row and column halves, asserting RAS and CAS signals to access the correct cell. It also issues refresh commands (auto-refresh or self-refresh modes) to maintain data integrity over time (e.g., full-array refresh within about 64 ms under normal temperatures).

Step-by-Step Solution:
Recognize DRAM addressing requires multiplexing: split address across time.Acknowledge leakage → periodic refresh needed.Therefore, the controller’s key roles are address multiplexing and refresh.

Verification / Alternative check:
DRAM datasheets and memory controller IP documentation specify RAS/CAS timing, tREFI scheduling, and refresh cycles, confirming these responsibilities.

Why Other Options Are Wrong:

• Address multiplexing and data selection: Omits refresh, which is essential.
• Data selection and refresh: Ignores multiplexed addressing central to DRAM.
• Data selection and CPU accessing: Vague; not the distinctive DRAM controller duties.

Common Pitfalls:

• Confusing DRAM refresh with cache coherence or DMA operations; they are unrelated.
• Assuming DRAM behaves like SRAM; DRAM requires controller-managed timing and refresh.

Final Answer:
Address multiplexing and the refresh operation