Static RAM (SRAM) cell structure In a static RAM device, what circuit element forms the fundamental storage cell for each bit?

Introduction / Context:
SRAM and DRAM store bits differently. Understanding the SRAM storage element explains why SRAM is fast and does not require refresh, yet is less dense than DRAM. This is crucial for cache memory design and performance analysis.

Given Data / Assumptions:

• SRAM holds data statically as long as power is applied.
• Typical SRAM cells use cross-coupled inverters forming a bistable latch (flip-flop behavior).
• No periodic refresh is required for data retention under power.

Concept / Approach:

An SRAM bit cell is essentially a tiny flip-flop (often implemented with six transistors in CMOS: two cross-coupled inverters and two access transistors). It stays in one of two stable states, representing 0 or 1, while enabled by word lines during read/write operations.

Step-by-Step Solution:

Verification / Alternative check:

Contrast with DRAM: a capacitor plus a transistor stores charge temporarily and needs refresh. With SRAM, the latching action holds the state indefinitely (under power).

Why Other Options Are Wrong:

• Diode/resistor alone cannot provide bistability for storage.
• Capacitor is DRAM’s storage element, not SRAM’s.

Common Pitfalls:

• Assuming “flip-flop” must mean a full edge-triggered FF; in SRAM, the cell is a minimalist latch with similar bistable behavior.

Final Answer:

flip-flop