Memory construction – widening data width using multiple RAM ICs How many 1K × 4 RAM chips are required to build a 1K × 8 memory subsystem (same address depth, doubled data width)?

Introduction / Context:
Designers often combine memory ICs to achieve a desired word width and depth. This question checks your ability to reason about arranging multiple narrow memories in parallel to widen the data bus while keeping the address space the same.

Given Data / Assumptions:

• Available IC: 1K × 4 (1,024 addresses, 4 data bits each).
• Target memory: 1K × 8 (1,024 addresses, 8 data bits each).
• Address depth must remain 1K; only width doubles from 4 to 8 bits.

Concept / Approach:
To double data width, place identical RAMs in parallel on the same address lines. One chip provides the lower 4 bits (D3..D0), the other provides the upper 4 bits (D7..D4). The chip enable and write enable signals are shared so both devices respond to the same address and control.

Step-by-Step Solution:

Verification / Alternative check:
Block-diagramming shows two chips tied A0..A9 in common, with data busses concatenated to form D7..D0. This is a standard technique in memory expansion.

Why Other Options Are Wrong:

• 4, 8, 16: These would oversupply width to 16, 32, or 64 bits respectively for a 1K depth, which is unnecessary.

Common Pitfalls:

• Confusing widening (parallel) with deepening (cascading addresses), which would multiply the address space rather than the word width.

Final Answer:
2