Address multiplexing (DRAM context): Evaluate the statement: “Address multiplexing is used to reduce the number of address lines.”

Introduction / Context:
As memory densities grew, packaging a separate pin for every address bit became impractical. DRAM solved this by multiplexing row and column addresses over the same physical pins, dramatically cutting package pin counts and cost. This question checks whether the learner recognizes the purpose of address multiplexing.

Given Data / Assumptions:

• We consider classic asynchronous DRAMs using RAS and CAS strobes.
• Row address and column address share the A0..An pins at different times.
• Goal: minimize package pins while still addressing large arrays.

Concept / Approach:
With N multiplexed pins, you can send R row bits and C column bits using the same pins: total addressability is 2^(R+C) while only max(R,C) pins are needed, not R+C pins. RAS latches the row; CAS latches the column. This halves the address pin count for square arrays and reduces it substantially for rectangular organizations, enabling high-density memories in economical packages.

Step-by-Step Solution:

Verification / Alternative check:
Compare pin counts: a 4M x 1 DRAM might use 11 address pins multiplexed (row 11 + column 11 → 22 effective bits) rather than 22 separate lines, confirming the reduction.

Why Other Options Are Wrong:

Common Pitfalls:
Assuming multiplexing is a timing optimization only; its primary benefit is pin reduction, with timing trade-offs handled by RAS/CAS cycles.

Final Answer:
Correct