Read cycle conditions for a typical RAM: A RAM places stored data on its outputs whenever Chip Select (CS) is active and Write Enable (WE) is inactive (read mode). Evaluate this statement.

Introduction / Context:
Understanding RAM control pins is crucial for timing diagrams, bus arbitration, and glue logic. In most SRAMs and DRAMs (after row/column addressing for DRAM), a read is recognized when the chip is selected and write is not requested, causing data to appear on the output drivers subject to output-enable gating.

Given Data / Assumptions:

• Conventional active-low control pins: CS (or CE), WE, and OE.
• During read: CS asserted, WE deasserted; OE typically asserted to enable the output buffers.
• Timing meets setup/hold and access-time constraints.

Concept / Approach:
For parallel SRAM: read cycle occurs when CS is active and WE is inactive; OE controls whether outputs drive the bus (tri-state when OE is inactive). For DRAM, after valid RAS/CAS sequences select the cell, read data is driven when write is not active. Hence, the simplified description is accurate for “placing data on outputs,” implicitly assuming OE is active as needed.

Step-by-Step Solution:

Verification / Alternative check:
Typical SRAM timing tables label tACC and tOE for access and output enable; both conditions are required for valid data appearance. DRAM read timing uses RAS/CAS with WE high (inactive) to produce data at Q/DQ pins.

Why Other Options Are Wrong:

Common Pitfalls:
Forgetting that outputs may be tri-stated when OE is inactive, even though a read cycle is in progress.

Final Answer:
Correct