Flash (simultaneous) ADC trade-off: What is the primary disadvantage of the simultaneous analog-to-digital converter (flash ADC) architecture?

Introduction / Context:
A flash, or simultaneous, analog-to-digital converter achieves extremely high conversion speed by comparing the input signal against many reference thresholds at the same instant. This design choice creates a well-known trade-off between speed and hardware complexity. The question asks you to identify the core disadvantage that limits flash ADC resolution and drives up silicon area and power.

Given Data / Assumptions:

• A flash ADC with n-bit resolution requires distinct threshold levels spanning the full-scale input range.
• Each threshold is implemented with a dedicated comparator and a resistor ladder network.
• The encoder converts a thermometer-style comparator output into binary.

Concept / Approach:
The comparator count in a flash ADC grows exponentially with resolution. Specifically, an ideal n-bit flash needs 2^n − 1 comparators. This directly impacts die area, input capacitance, power consumption, offset trimming requirements, and layout complexity. Because of this scaling, practical flash converters typically target modest resolutions (for example, 6–8 bits) where the comparator count remains manageable, while still delivering exceptional sampling rates.

Step-by-Step Solution:

Verification / Alternative check:
Survey architectures across ADC families: SAR and pipeline avoid exponential comparator growth by making sequential or staged decisions, trading some speed for lower hardware complexity. This confirms that comparator count is the flash ADC bottleneck.

Why Other Options Are Wrong:

Common Pitfalls:
Confusing digital output bus width with internal comparator count; assuming speed is a disadvantage rather than an advantage for flash designs.

Final Answer:
the large number of comparators required to represent a reasonable-sized binary number