Difficulty: Easy
Correct Answer: Incorrect
Explanation:
Introduction: Not all shift registers support both serial shifting and parallel loading. The SN74164 device is a classic serial-in/parallel-out (SIPO) register: it shifts data in serially and presents the accumulated bits at parallel outputs; it does not provide a “parallel load” control that captures an entire word at once. This question asks you to judge a statement that incorrectly attributes a parallel-load capability to the 74164.Given Data / Assumptions:
Concept / Approach: A true parallel load requires per-bit data inputs and a load control that selects those inputs at a clock edge. The 74164 exposes no per-bit data bus for parallel capture; it accepts serial data only. Therefore, any wording about “parallel enable LOW” for synchronous parallel loading is incompatible with the device’s feature set and is false.Step-by-Step Solution:
Check the pinout: only serial inputs (A and B) feed the internal chain.Check controls: there is no LOAD/SHIFT select; only clock and asynchronous clear exist.Conclude: parallel loading is not supported; the claim is invalid regardless of clock edge polarity.Verification / Alternative check:
Compare with a universal shift register (e.g., 74194/74195) which does provide a SHIFT/LOAD control and parallel inputs; 74164 does not.Why Other Options Are Wrong:
Correct: Would require a feature the 74164 lacks.True only with external gating: External logic can preload lines but still enters serially; not parallel load.Depends on asynchronous clear: Clear resets the chain; it is unrelated to parallel capture.Common Pitfalls:
Confusing SIPO devices (74164) with universal shift registers (74195).Thinking “parallel outputs” implies “parallel load.” These are different features.Final Answer:
Incorrect
Discussion & Comments