Difficulty: Easy
Correct Answer: On the next active clock edge
Explanation:
Introduction:
The 74195 is a universal shift register supporting both serial shifting and parallel loading via a SHIFT/LOAD control input. Understanding whether the parallel load is synchronous or asynchronous is essential for correct timing design.
Given Data / Assumptions:
Concept / Approach:
In parallel load mode, each stage takes its input from the parallel data bus. However, loading occurs on the defined active clock edge (typically the rising edge) so that all bits are captured simultaneously and deterministically. Therefore, outputs do not change “immediately”; they update synchronously on the next clock edge while SHIFT/LOAD remains LOW.
Step-by-Step Solution:
Verification / Alternative check:
Why Other Options Are Wrong:
Common Pitfalls:
Final Answer:
Discussion & Comments