Shift-register delay selection: An 8-bit serial-in/parallel-out (SIPO) shift register is clocked at 4 MHz (Tclk = 0.25 µs) and is used to delay a serial digital signal by exactly 1.25 µs. Which parallel tap (QA through QH) provides the output with the required delay?

Introduction / Context:Serial-in/parallel-out (SIPO) shift registers are frequently used to create precise, clock-synchronous delays. Each stage holds the input bit for one clock period, so selecting the correct tap provides a deterministic delay useful in timing alignment, serialization, de-serialization, and pulse stretching.

Given Data / Assumptions:

• Register type: 8-bit SIPO with taps QA (stage 1) through QH (stage 8).
• Clock frequency fclk = 4 MHz, so Tclk = 1 / 4 MHz = 0.25 µs.
• Required total delay = 1.25 µs relative to the serial input bit entering the register.
• Standard stage labeling: QA is the first stage, QH is the eighth.

Concept / Approach:In a SIPO, a bit appears at stage n after n clock edges. Thus, the delay at tap Qn equals n * Tclk. Choose n so that n * 0.25 µs = 1.25 µs. The integer n that satisfies this is n = 5, corresponding to the fifth stage (QE).

Step-by-Step Solution:

Verification / Alternative check:List delays per tap: QA=0.25 µs, QB=0.50 µs, QC=0.75 µs, QD=1.00 µs, QE=1.25 µs, QF=1.50 µs, QG=1.75 µs, QH=2.00 µs. The required delay matches QE exactly.

Why Other Options Are Wrong:

• QF: 6 * 0.25 µs = 1.50 µs (too large).
• QG: 7 * 0.25 µs = 1.75 µs (too large).
• QH: 8 * 0.25 µs = 2.00 µs (too large).

Common Pitfalls:Off-by-one mistakes in stage numbering; confusing SIPO stage index with bit significance; ignoring that each stage adds exactly one Tclk of latency. Always confirm the device's pinout for QA–QH mapping.

Final Answer:QE