Parallel-in/serial-out timing: A 4-bit parallel-in/serial-out (PISO) shift register is loaded with a binary number using the parallel-load control. After the parallel load occurs, how many clock pulses are required before the first bit of the serialized sequence appears at the serial output?

Introduction / Context:
PISO (parallel-in/serial-out) registers convert a parallel word into a serial bitstream. Understanding when the first bit becomes available is essential for designing serializers, time-division multiplexers, and interface adapters where precise cycle-by-cycle timing is critical.

Given Data / Assumptions:

• Device: 4-bit PISO shift register.
• A valid parallel load cycle places the word into the internal stages.
• Serial output taps the register stage designated for the first transmitted bit (often MSB).
• Standard synchronous design: load and shift controls are distinct.

Concept / Approach:
On a parallel load, each internal stage immediately holds its corresponding bit. Because the serial output is wired to the stage that is transmitted first, that bit is already present at the output right after the load completes. No additional shift clock is required to make the first bit appear; the next clocks shift the remaining bits out in order.

Step-by-Step Solution:

Verification / Alternative check:
Consult generic PISO timing: the first bit is valid post-load; tCO (clock-to-output) or load-to-output timing applies, not an extra shift. Only if the design specifies LSB-first with a different tap would the same rule apply to that designated stage.

Why Other Options Are Wrong:

• 1, 2, 3 clocks: These assume a shift is needed to expose the first bit, which contradicts the PISO's parallel load behavior.

Common Pitfalls:
Confusing PISO with SISO behavior; overlooking that the output is hardwired to one stage that already contains a valid bit immediately after load; misreading the data sheet's sequence diagram.

Final Answer:
0