Two’s-complement practice: In a 16-bit microcomputer, what is the 2’s-complement representation of −24?

Introduction / Context:The two’s-complement system encodes signed integers so that addition and subtraction use the same binary adder. Negative values are formed by inverting all bits of the positive magnitude (one’s complement) and adding 1. This exercise reinforces that workflow in a 16-bit context.

Given Data / Assumptions:

• Word size: 16 bits.
• Target value: −24.
• We assume standard two’s-complement arithmetic with sign extension.

Concept / Approach:Procedure: write +24 in 16-bit binary, invert every bit to get the one’s complement, then add 1 to obtain the two’s complement. The high bit will be 1 to indicate a negative number in two’s complement.

Step-by-Step Solution:Write +24: 24 = 16 + 8 → 0000 0000 0001 1000.Invert bits (one’s complement): 1111 1111 1110 0111.Add 1: 1111 1111 1110 0111 + 0000 0000 0000 0001 = 1111 1111 1110 1000.Thus, −24 = 1111 1111 1110 1000 (two’s complement, 16-bit).

Verification / Alternative check:Add 1111 1111 1110 1000 to +24 and confirm wraparound to 0 with carry out discarded: result equals 0, validating the encoding.

Why Other Options Are Wrong:0000 0000 0001 1000: this is +24, not −24.1111 1111 1110 0111: one’s complement only; missing the +1 step.0001 0001 1111 0011: unrelated pattern; not derived from the two’s-complement steps.None: incorrect because option (c) is correct.

Common Pitfalls:Forgetting to add 1 after inverting, or failing to maintain the full 16-bit width with proper leading ones for negative numbers.

Final Answer:1111 1111 1110 1000