In synchronous digital systems, a single periodic coordination signal is sent to every flip-flop to synchronize state changes. What is this common signal called?

Introduction / Context:
Synchronous digital design relies on a timing reference so that registers (flip-flops) capture data simultaneously at well-defined instants. This global coordination ensures predictable behavior across complex pipelines, state machines, and buses. The coordinating signal is central to the design methodology.

Given Data / Assumptions:

• The system uses edge- or level-triggered flip-flops.
• All sequential elements receive a shared timing reference.
• We need the standard name of that reference signal.

Concept / Approach:
The “clock” is a periodic waveform that defines when state is sampled or transferred. On rising or falling edges (edge-triggered) or during active levels (level-sensitive latches), flip-flops capture inputs and update outputs. Distribution networks and clock trees are engineered to minimize skew and jitter so all parts of the system agree on timing.

Step-by-Step Solution:
Identify the element: flip-flops require a timing reference.Name the periodic, systemwide timing signal.Answer: the common signal is the clock.

Verification / Alternative check:
Observe any synchronous design: registers change on the same edge; asynchronous inputs must be synchronized to the clock domain to avoid metastability.

Why Other Options Are Wrong:
Latch: a level-sensitive storage element, not the system timing signal.Master/Slave: describe roles in certain flip-flop structures, not the global timing wave.None: incorrect because “clock” is the standard term.

Common Pitfalls:
Confusing clocks with enables or resets; overlooking clock domain crossing issues and the need for synchronizers.

Final Answer:
clock