JTAG-based test methods Which of the following test procedures specifically uses the IEEE 1149.1 JTAG standard?

Introduction / Context:
JTAG (IEEE 1149.1) defines a standard interface and architecture for testing and debugging integrated circuits. Understanding which board-level test techniques rely on JTAG helps engineers plan for design-for-test (DFT), select connectors, and script automated tests in manufacturing.

Given Data / Assumptions:

• Boundary-scan architecture inserts scan cells at I/O pins of compliant devices.
• The JTAG TAP (Test Access Port) provides standardized pins: TCK, TMS, TDI, TDO (and optionally TRST).
• EXTEST is a JTAG instruction used within the boundary-scan procedure.

Concept / Approach:
Among the options, “Boundary scan” is the board-level test methodology explicitly defined by IEEE 1149.1. It enables interconnect testing without physical probes by shifting test data into boundary cells and capturing responses. “EXTEST” is an instruction within boundary scan (not a procedure by itself). Bed-of-nails and flying-probe are physical probing methods, independent of JTAG, although they may be used in combination with JTAG on some lines.

Step-by-Step Solution:

Verification / Alternative check:
IEEE 1149.1 documentation describes boundary-scan test logic, instruction register, and opcodes (including EXTEST), confirming that boundary scan is the JTAG-based test methodology.

Why Other Options Are Wrong:

• Bed-of-nails / Flying probe: Mechanical probing fixtures; not defined by the JTAG standard.
• EXTEST: A single JTAG instruction used during boundary-scan tests, not the procedure name.

Common Pitfalls:
Conflating a specific JTAG opcode (EXTEST) with the overall standardized method (boundary scan). Also, assuming physical ICT/FP testing equals JTAG testing—many boards use both but they are distinct techniques.

Final Answer:
Boundary scan