CPLD composition — internal building blocks Within a complex programmable logic device (CPLD), the PAL-like simple PLD structures are organized into units commonly called:

Introduction / Context:
CPLDs scale up the PAL/SPLD concept by combining multiple logic blocks with extensive interconnect. The terminology for these building blocks is essential when reading datasheets and fitting logic during synthesis.

Given Data / Assumptions:

• CPLD = multiple logic blocks inside a single chip.
• Each block houses logic resources and registers.
• Vendors may vary names slightly, but “macrocell” is industry-standard.

Concept / Approach:
A macrocell typically contains the OR-summed product terms, an optional register (flip-flop), output enable control, and programmable polarity. Many macrocells aggregate into logic array blocks (LABs), which are then interconnected via a programmable routing matrix to form the full CPLD.

Step-by-Step Solution:

Verification / Alternative check:
Vendor documentation (e.g., Altera/Intel MAX7000, Xilinx XC9500) consistently uses the term macrocell for the basic logic/register element.

Why Other Options Are Wrong:

• Microcells: not standard nomenclature for CPLDs.
• AND/OR arrays and fuse-link arrays: these are structural components, not the encapsulated functional unit name.

Common Pitfalls:
Confusing macrocell vs. LAB naming; macrocells are the per-output logic units, LABs are groups of macrocells.

Final Answer:
macrocells