Difficulty: Easy
Correct Answer: timer bus
Explanation:
Introduction / Context:
Microprocessor systems communicate over well-defined buses. Knowing the canonical bus types clarifies system diagrams and helps troubleshoot hardware issues involving signal lines and timing.
Given Data / Assumptions:
Concept / Approach:
The data bus transfers data values; the address bus selects memory or I/O locations; the control bus carries control signals (e.g., read/write strobes, clock, interrupts). ”Timer bus” is not a standard category; timers are peripherals connected via the existing buses.
Step-by-Step Solution:
List canonical buses: data, address, control.Check ”timer bus”: not part of the canonical set; timers are mapped on the existing buses.Therefore, ”timer bus” is not a standard bus type.Select: timer bus.
Verification / Alternative check:
Reference any introductory computer organization text: the three-bus model (address, data, control) is foundational and widely taught.
Why Other Options Are Wrong:
Data, address, control buses are essential and ubiquitous in processor architectures.
Common Pitfalls:
Mistaking a peripheral function (timers) for a separate interconnect category.
Final Answer:
timer bus
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