Voltage-divider biased common-emitter (CE) stage: The small-signal AC input resistance Rin seen at the base is made up of which parallel combination?

Introduction / Context:
In a voltage-divider biased CE amplifier, two resistors provide a stable DC bias to the base. For AC analysis, the source “sees” not only the transistor’s base input resistance but also the bias network. Correctly identifying Rin is critical for signal source matching and gain prediction.

Given Data / Assumptions:

• Voltage-divider bias using R1 (from VCC to base) and R2 (from base to ground).
• Small-signal AC analysis around the bias point.
• Emitter bypass capacitor, if present, does not remove the divider from the input path.
• r_pi (also written h_ie) models the transistor’s small-signal base resistance.

Concept / Approach:
From the perspective of the AC source tied to the base, R1 connects to a low-impedance supply node (AC ground), R2 connects to ground, and r_pi connects into the transistor. All three terminate to AC ground, so they appear in parallel. Therefore, the net input resistance is Rin ≈ R1 || R2 || r_pi.

Step-by-Step Solution:

Verification / Alternative check:
Compute with example values (e.g., R1 = 100 kΩ, R2 = 50 kΩ, r_pi = 5 kΩ): Rin ≈ (100k || 50k || 5k) ≈ 4.2 kΩ, showing that r_pi often dominates when it is much smaller than the divider resistances.

Why Other Options Are Wrong:

• Series combination (option b) misrepresents AC grounding of VCC.
• “Only r_pi” (option c) ignores the real loading of the divider.
• “R1 || R2 only” (option d) neglects the transistor’s base input path.

Common Pitfalls:
Forgetting to ground the supply in AC models and overlooking how bias resistors load the source, reducing Rin and the stage’s effective gain.

Final Answer:
Rin = R1 || R2 || r_pi.