Why use two's complement for signed integers? Select the primary advantage of the 2's complement number system for representing signed binary integers in digital hardware.

Introduction / Context:
Two’s complement is the dominant signed-integer representation in general-purpose processors. Its popularity stems from the way it simplifies hardware design, especially for subtraction, overflow detection, and representation of zero and negative values without dual “+0/−0.”

Given Data / Assumptions:

• We are comparing signed encodings (signed magnitude, one’s complement, two’s complement).
• Goal: identify a key computational advantage in hardware.
• Standard binary adders are available.

Concept / Approach:
In two’s complement, subtraction A − B is implemented as A + (two’s complement of B). The same adder circuit performs both addition and subtraction by conditionally inverting B and adding 1 via the carry-in. This unifies the hardware path and eliminates the need for a separate subtractor. Additional benefits include a unique zero and straightforward overflow rules.

Step-by-Step Solution:

Verification / Alternative check:
Examine an ALU control table: addition and subtraction share the adder core, differing only by operand inversion and carry-in setting.

Why Other Options Are Wrong:

Common Pitfalls:
Confusing one’s complement with two’s complement (one’s complement has +0 and −0 representations).

Final Answer:
can perform subtraction by performing addition