Question 1

Two’s complement addition (8-bit): Add 11110010 and 11110011. First identify each 8-bit number's decimal sign and magnitude, then compute their decimal sum.

Accepted Answer

Introduction / Context: Two’s complement is the dominant signed binary representation used by processors. Mastery involves recognizing negative values, converting between binary and decimal, and performing addition with correct overflow interpretation. Given Data / Assumptions: Word size: 8 bits. Operands: 11110010 and 11110011. Interpretation: two’s complement signed integers. Concept / Approach: For two’s complement: if the MSB is 1, the value is negative and equals the negative of the two’s complement magnitude. To find magnitude: invert bits, add 1. Addition of two’s complement numbers uses ordinary binary addition; discard any carry beyond 8 bits, then interpret the result with sign bit. Step-by-Step Solution: Number A = 11110010 → MSB = 1 → negative. Invert: 00001101; add 1 → 00001110 = 14 → A = –14.Number B = 11110011 → MSB = 1 → negative. Invert: 00001100; add 1 → 00001101 = 13 → B = –13.Sum: –14 + –13 = –27 (decimal).Binary add (optional check): 11110010 + 11110011 = 1 11100101 (9-bit). Discard carry → 11100101. Invert to check magnitude: 00011010; add 1 → 00011011 = 27; MSB 1 → –27. Verification / Alternative check: Decimal arithmetic confirms –27. The sign bit of 11100101 is 1 and magnitude check yields 27, consistent with –27. No signed overflow occurred here because adding two negatives cannot overflow into positive in 8-bit unless magnitude exceeds range, which it does not (range is –128 to +127). Why Other Options Are Wrong: –113 and –114; 227: Magnitudes misread and sum sign incorrect. –27 and –13; 40: First operand’s interpretation wrong; sum inconsistent. –11 and –16; –27: Operand magnitudes misdecoded. Common Pitfalls: Forgetting to invert then add 1 when decoding negatives; mishandling end carry; misinterpreting the sign bit after addition. Final Answer: –14 and –13; –27

Question 2

Compute –11 + (–2) using 8-bit two’s complement. Which 8-bit two’s-complement result is obtained?

Accepted Answer

Introduction / Context: Binary arithmetic with signed numbers relies on two’s complement encoding. This question checks your ability to encode negatives and perform binary addition correctly within a fixed word size (8 bits). Given Data / Assumptions: Operands: –11 and –2. Word length: 8 bits. Two’s complement arithmetic; discard carry out of MSB. Concept / Approach: To represent –N in two’s complement: write N in binary, invert all bits, then add 1. Add using binary rules; the carry beyond bit 7 is dropped. Interpret the final 8 bits as two’s complement. Step-by-Step Solution: +11 = 0000 1011 → invert 1111 0100 → add 1 → 1111 0101 (this is –11).+2 = 0000 0010 → invert 1111 1101 → add 1 → 1111 1110 (this is –2).Add: 1111 0101 + 1111 1110 = 1 1111 0011 (9-bit). Discard carry → 1111 0011.Interpret: MSB = 1 → negative. Magnitude check: invert 0000 1100; add 1 → 0000 1101 = 13 → result = –13, which matches –11 + –2 = –13. Verification / Alternative check: Decimal check: –11 + –2 = –13; result encoding 1111 0011 corresponds to –13 in 8-bit two’s complement. Range –128…+127 supports this result without overflow. Why Other Options Are Wrong: 1110 1101 / 1110 1001 / 1111 1001: These bit patterns decode to other negative values (not –13) and do not match the arithmetic. Common Pitfalls: Not discarding the end carry; forgetting the invert+1 rule; mixing sign-magnitude with two’s complement decoding. Final Answer: 1111 0011

Question 3

4-bit parallel adder design: What is the purpose of fast-carry / look-ahead carry circuitry used in most 4-bit parallel adders?

Accepted Answer

Introduction / Context: Adder speed is often limited by carry propagation. Ripple-carry adders propagate carries sequentially, creating cumulative delay. Look-ahead carry logic anticipates carries in parallel, greatly improving performance in arithmetic units. Given Data / Assumptions: Target: 4-bit parallel adder. Technique: carry look-ahead (fast carry). Goal: compare timing behavior vs. ripple carry. Concept / Approach: Carry look-ahead computes generate (G) and propagate (P) signals for each bit, then forms carries for all stages using combinational logic rather than waiting for serial propagation. This reduces overall adder delay from O(n) to approximately O(log n) levels of logic (for hierarchical designs). Step-by-Step Solution: Define bit signals: G_i = A_i * B_i, P_i = A_i + B_i.Compute carries in parallel: C_1, C_2, C_3, C_4 derived from G/P and C_0.Sum outputs S_i = A_i ⊕ B_i ⊕ C_i determined once carries are known quickly. Verification / Alternative check: Timing analysis shows look-ahead reduces the worst-case chain delay inherent in ripple adders. Empirically, 74xx-series look-ahead generators (e.g., 74182) speed up multi-nibble additions by precomputing carries. Why Other Options Are Wrong: increase ripple delay: Opposite of intent. add a 1 to complemented inputs: Not the function of carry look-ahead. determine sign and magnitude: That is post-addition interpretation, not carry acceleration. Common Pitfalls: Assuming look-ahead changes arithmetic results; it only changes timing. Also confusing propagate vs. generate roles. Final Answer: reduce propagation delay

Question 4

Binary addition practice: Add decimal 26 and 27 in binary and choose the correct binary sum.

Accepted Answer

Introduction / Context: Converting between decimal and binary and then performing binary addition reinforces number-system fluency vital for digital logic, encoding, and low-level software work. Given Data / Assumptions: Operands: 26 and 27 (decimal). Required: binary sum. Concept / Approach: Convert each decimal number to binary, perform column-wise binary addition with carries, and then confirm by reconverting the result back to decimal. Step-by-Step Solution: 26 (decimal) = 16 + 8 + 2 = 11010 (binary).27 (decimal) = 16 + 8 + 2 + 1 = 11011 (binary).Add: 11010 + 11011 = 110101 (binary).Check: 110101 = 32 + 16 + 4 + 1 = 53 (decimal); 26 + 27 = 53 → matches. Verification / Alternative check: Decimal calculation confirms 53. Long addition in binary shows carries from lower bits forming the sixth bit in the result, which is expected for sums exceeding 31. Why Other Options Are Wrong: 111010 (58), 110110 (54), 101011 (43): Do not equal 53; arithmetic mismatch. Common Pitfalls: Dropping a carry when adding the least significant bits; mis-conversion of decimal to binary (especially around the 16 and 8 positions). Final Answer: 110101

Question 5

Binary long division: Divide 1100010 (binary) by 0101 (binary 5). What is the decimal remainder of the division?

Accepted Answer

Introduction / Context: Binary division mirrors decimal long division but uses base-2 arithmetic. Understanding remainders is useful for modulus operations, checksums, and cyclic redundancy computations. Given Data / Assumptions: Dividend: 1100010₂. Divisor: 0101₂ (which equals 5₁₀). Asked: decimal value of the remainder. Concept / Approach: You can either perform binary long division directly or convert to decimal to quickly find the remainder, since modulo is base-independent for exact integer values: remainder(98, 5) = 98 mod 5. Step-by-Step Solution: Convert dividend: 1100010₂ = 64 + 32 + 2 = 98₁₀.Convert divisor: 0101₂ = 5₁₀.Compute remainder: 98 mod 5 = 5*19 = 95; 98 – 95 = 3.Therefore, remainder = 3 (decimal). Verification / Alternative check: Binary long division also yields a remainder of 0011₂, which is 3₁₀. Either path confirms the same result, validating the conversion and arithmetic. Why Other Options Are Wrong: 2, 4, 6: Not equal to 98 mod 5; these would be correct only for different dividends. Common Pitfalls: Misreading the dividend bits (especially leading zeros) or miscalculating place values when converting to decimal. Always double-check binary weights (…32, 16, 8, 4, 2, 1). Final Answer: 3

Question 6

ALU control concept: The selector (control) inputs to an arithmetic-logic unit determine what aspect of its operation?

Accepted Answer

Introduction / Context: An arithmetic-logic unit (ALU) is the computational heart of a processor or digital datapath. Control or selector lines command the ALU to perform specific operations on its inputs, enabling instruction execution and micro-operations. Given Data / Assumptions: We consider a generic multi-function ALU with control lines (e.g., S₀…Sₙ). Inputs A and B are operand words; flags may reflect results. Concept / Approach: ALU selector inputs choose among available functions: addition, subtraction (via two’s complement), increment, decrement, logical AND/OR/XOR/NOT, shifts/rotates (if integrated), etc. They do not select the chip itself, the data source, or the system clock rate; those are managed by other subsystems (decoder, multiplexers, clock generator). Step-by-Step Solution: Identify role of selector lines: choose operation among arithmetic and logic functions.Exclude alternatives: IC selection is via chip select; data word selection via multiplexers; clock frequency via clock circuitry, not ALU selectors.Therefore, the correct mapping is: selector inputs → chosen arithmetic/logic function. Verification / Alternative check: Examine classic ALUs (e.g., 74181). Control bits determine whether the unit performs arithmetic vs. logic operations and which specific function, confirming the principle. Why Other Options Are Wrong: selection of the IC: Handled by chip-select, not ALU function selectors. data word selection: Controlled by multiplexers and register enables. clock frequency: Provided by the system clock, independent of ALU function codes. Common Pitfalls: Confusing ALU function control with instruction decode or bus selection signals; remember the ALU only transforms input data according to these selector codes. Final Answer: arithmetic or logic function

Question 7

Two’s complement subtraction setup: To compute 43 − 15 in binary by addition, which 6-bit two’s-complement code should be added to 43 to represent “minus 15”?

Accepted Answer

Introduction / Context: Digital systems perform subtraction by adding the two’s complement of the subtrahend. Selecting the correct two’s-complement pattern is crucial for correct results and for understanding how ALUs handle subtraction internally. Given Data / Assumptions: Operation: 43 − 15. Assume 6-bit words (sufficient since 43 is 101011₂ and 15 is 001111₂). Task: choose the 6-bit two’s complement of 15 to add to 43. Concept / Approach: For two’s complement: –N = invert(all bits of N) + 1. Represent 15 in 6 bits, form its two’s complement, and identify the correct option. Step-by-Step Solution: 15 (decimal) in 6 bits = 00 1111 → 001111.Invert: 110000.Add 1: 110000 + 000001 = 110001. This is the 6-bit code for –15.Therefore, to compute 43 − 15, add 43 + 110001 (the two’s complement of 15). Verification / Alternative check: Perform the addition: 43 (101011) + 110001 = 1 011100 (ignore carry) = 011100 = 28, which equals 43 − 15, confirming the correctness. Why Other Options Are Wrong: 110000: Missing the +1 step; this is one’s complement of 15, not two’s. 101011 / 011100: These are unrelated values (43 and 28, respectively), not the needed complement. Common Pitfalls: Forgetting to add 1 after inversion; using too few bits so that sign is lost; misreading leading zeros in fixed-width formats. Final Answer: 110001

Question 8

Adder fundamentals: Name the two basic adder building blocks used in digital circuits.

Accepted Answer

Introduction / Context: Adders are foundational to arithmetic units, counters, checksum generators, and digital signal processing blocks. Understanding the elemental adder cells clarifies how wider adders and ALUs are constructed. Given Data / Assumptions: We seek the canonical names of the smallest adder units. System uses binary arithmetic with carry handling. Concept / Approach: A half adder adds two single-bit operands and produces a sum and a carry (no carry-in). A full adder extends this by including a carry-in input, allowing chaining to create multi-bit ripple or look-ahead adders. Parallel adders are assemblies of full adders; they are not a different “basic type.” Step-by-Step Solution: Half adder: inputs A, B; outputs Sum = A ⊕ B, Carry = A * B.Full adder: inputs A, B, Cin; outputs Sum = A ⊕ B ⊕ Cin; Cout = majority(A, B, Cin).Chain N full adders to form an N-bit parallel adder (ripple or with carry acceleration). Verification / Alternative check: Standard logic libraries and textbooks specify these two as primitive adder cells; all larger adders decompose to these functions. Why Other Options Are Wrong: half adder and parallel adder: “Parallel adder” is a composition of full adders, not a primitive. asynchronous and synchronous: Timing classifications, not adder cell types. one’s complement and two’s complement: Number representations, not adder circuit types. Common Pitfalls: Confusing architectural composition (“parallel adder”) with primitive cells; conflating numeric representations with hardware blocks. Final Answer: half adder and full adder

Question 9

Binary multiplication practice When multiplying the decimal numbers 13 × 11 using binary arithmetic (13 = 1101₂ and 11 = 1011₂), what is the third partial product generated during the shift-and-add process?

Accepted Answer

Introduction / Context: This problem checks your understanding of binary multiplication by hand, specifically identifying the intermediate (partial) products that arise when a multiplicand is conditionally shifted and added based on the multiplier bits. Given Data / Assumptions: Multiplicand: 13₁₀ = 1101₂. Multiplier: 11₁₀ = 1011₂ (bits processed from least significant to most significant). Standard shift-and-add binary multiplication procedure. Concept / Approach: For each bit of the multiplier (from LSB to MSB), write a partial product: either the multiplicand left-shifted by the bit position (if that bit is 1) or a row of zeros (if that bit is 0). The “third partial product” corresponds to the third processed bit of the multiplier (bit index 2, counting from 0 at the LSB). Step-by-Step Solution: Write numbers: multiplicand = 1101₂, multiplier = 1011₂.Bit 0 (LSB) of multiplier = 1 → 1st partial product = 1101.Bit 1 of multiplier = 1 → 2nd partial product = 11010 (one left shift).Bit 2 of multiplier = 0 → 3rd partial product = 0000 (all zeros, two-position row).Bit 3 of multiplier = 1 → 4th partial product = 1101000 (three left shifts). Verification / Alternative check: If the third multiplier bit is zero, no contribution occurs at that stage, so the corresponding row must be zeros, confirming the choice. Why Other Options Are Wrong: 100000 / 100001 / 1011: These represent nonzero rows; they would imply a 1 in the third multiplier bit, which is not the case. Common Pitfalls: Counting partial products from the MSB side or forgetting that a 0 multiplier bit yields an all-zero partial product. Final Answer: 0000

Question 10

Two's-complement limits For an 8-bit two's-complement binary number, what is the numerical range represented (inclusive)?

Accepted Answer

Introduction / Context: Understanding the representable range of two's-complement integers is fundamental for overflow checks, embedded systems programming, and digital arithmetic design. Given Data / Assumptions: Word size n = 8 bits. Two's-complement representation with one sign bit. Concept / Approach: The two's-complement range is: minimum = −2^(n−1), maximum = +2^(n−1) − 1. This asymmetry arises because there is only one representation for zero, leaving an extra negative value. Step-by-Step Solution: Compute min: −2^(8−1) = −2^7 = −128.Compute max: +2^(8−1) − 1 = +2^7 − 1 = +127.Therefore, range is −128 to +127 (base 10). Verification / Alternative check: List extreme bit patterns: 10000000₂ = −128; 01111111₂ = +127, confirming the range. Why Other Options Are Wrong: Options showing +128 as representable are incorrect in two's complement; +128 requires 9 bits. Common Pitfalls: Confusing sign-magnitude with two's complement or assuming symmetry about zero. Final Answer: –12810 to +12710

Question 11

Counting single-bit subtraction cases How many distinct basic one-bit binary subtraction operations (A − B, without borrow-in) are possible?

Accepted Answer

Introduction / Context: Binary subtraction at the single-bit level underpins subtractor design and the generation of borrow signals in arithmetic logic units. Given Data / Assumptions: Single-bit operands A and B ∈ {0,1}. No borrow-in (Bin = 0). Outputs: difference bit D and borrow-out Bout. Concept / Approach: With two binary inputs A and B, there are 2 × 2 = 4 input combinations. Each combination yields a defined (D, Bout). Step-by-Step Solution: List cases: (A,B) = (0,0), (0,1), (1,0), (1,1).Compute D,Bout for each: 0−0→D=0,Bout=0; 0−1→D=1,Bout=1; 1−0→D=1,Bout=0; 1−1→D=0,Bout=0.Thus, there are four distinct basic operations. Verification / Alternative check: Truth table of a one-bit subtractor confirms four rows. Why Other Options Are Wrong: 3, 2, 1: underestimate the number of input combinations. Common Pitfalls: Accidentally including borrow-in changes the table size, but the question specifies basic operations without borrow-in. Final Answer: 4

Question 12

Counting subtraction input combinations For one-bit binary subtraction without borrow-in, how many distinct input combinations (A,B) exist?

Accepted Answer

Introduction / Context: Designing a one-bit subtractor begins with enumerating all input combinations. This ensures complete coverage for truth-table-based or Boolean design. Given Data / Assumptions: Inputs A and B are single bits. No borrow-in. Concept / Approach: Two binary inputs yield 2^2 = 4 distinct combinations. Each combination defines the resulting difference and borrow-out. Step-by-Step Solution: Compute total combinations: 2 inputs → 2^2 = 4.Enumerate: (0,0), (0,1), (1,0), (1,1).Hence, there are four basic combinations. Verification / Alternative check: Cross-check with a subtractor truth table; it contains four rows for A,B without borrow-in. Why Other Options Are Wrong: 3, 2, 1: do not account for all A,B permutations. Common Pitfalls: Confusing “operations” with “results” or mixing in borrow-in, which doubles the rows. Final Answer: 4

Question 13

Building a full adder from half adders: Evaluate the claim: “Two half adders can be combined to form a full adder with no additional gates.” State whether the statement is valid.

Accepted Answer

Introduction / Context: Adder construction is a staple topic in digital design. A full adder sums three one-bit inputs (A, B, Cin) to produce Sum and Cout. A common synthesis is to use two half adders plus an OR gate. This question tests whether you recall the exact gate count and interconnection required. Given Data / Assumptions: Half adder produces Sum = A XOR B and Carry = A AND B. Full adder requires Sum = A XOR B XOR Cin and Cout = majority(A,B,Cin). Standard gates (no wired-logic assumptions). Concept / Approach: Construct a full adder by: (1) Half-adder #1 on A and B → S1 = A XOR B, C1 = A AND B. (2) Half-adder #2 on S1 and Cin → Sum = S1 XOR Cin, C2 = S1 AND Cin. (3) Final carry Cout = C1 OR C2. Therefore, two half adders alone do not complete the full adder; an additional OR gate is required to combine the two carry terms. Step-by-Step Solution: Compute S1 = A XOR B; C1 = A AND B.Compute Sum = S1 XOR Cin; C2 = S1 AND Cin.Compute Cout = C1 OR C2 (additional gate).Hence, two half adders by themselves are insufficient. Verification / Alternative check: Truth-table verification of carry terms shows Cout true whenever at least two of A, B, Cin are 1. C1 OR C2 realizes this, requiring the final OR gate beyond the two half adders. Why Other Options Are Wrong: Correct: Omits the necessary OR gate. Wired-OR/XOR–XNOR sharing/fan-out only: These are implementation details that do not remove the logical need to combine carry terms. Common Pitfalls: Forgetting the final carry combination stage; assuming the second half adder magically produces the final Cout directly without merging intermediate carries. Final Answer: Incorrect

Question 14

Adder acceleration techniques: Confirm or refute the statement: “A technique to accelerate parallel addition by bypassing the ripple delay of carry propagation is called fast carry, or look-ahead carry.”

Accepted Answer

Introduction / Context: Ripple-carry adders are simple but slow because each bit’s carry must wait for the previous bit to resolve. Carry look-ahead logic computes carry signals in parallel using propagate/generate terms, dramatically reducing addition latency. The statement probes your understanding of this well-known speedup method. Given Data / Assumptions: Parallel adder with multiple bit-slices. Desire to reduce the dependency chain of carries. Use of propagate (P) and generate (G) terms to predict carries early. Concept / Approach: Carry look-ahead (also called fast carry) forms expressions such as C1 = G0 OR (P0 * Cin), C2 = G1 OR (P1 * G0) OR (P1 * P0 * Cin), and so on, removing the serial dependence on intermediate sums. Hardware blocks (e.g., 74xx look-ahead generators) compute several carries at once, enabling adders with logarithmic-like carry depth compared to linear ripple paths. Step-by-Step Solution: Define per-bit propagate P_i = A_i XOR B_i and generate G_i = A_i AND B_i.Form carry equations in parallel using OR and AND combinations.Compute all carries rapidly, then compute final Sum_i = P_i XOR C_i.This bypasses the ripple delay, achieving “fast carry.” Verification / Alternative check: Standard digital design texts and classic MSI devices (e.g., 74LS181 with 74LS182 fast-carry) demonstrate significant speed gains by using carry look-ahead rather than ripple propagation. Why Other Options Are Wrong: Incorrect / serial adders / sub-1 MHz only / fan-in only: These either restrict the concept improperly or confuse architectural speed limits with the core idea of parallel carry computation. Common Pitfalls: Assuming carry look-ahead eliminates all delay; it reduces but does not make delay zero. Large adders often use hierarchical or carry-select structures to scale further. Final Answer: Correct

Question 15

Signed number representations in digital systems: In sign–magnitude representation, a signed binary number reserves one dedicated sign bit, while the remaining bits represent the magnitude. Evaluate this statement in the context of common signed for…

Accepted Answer

Introduction / Context: Digital electronics and computer arithmetic use several ways to encode negative integers. The two most frequently discussed are sign–magnitude and two's complement. The statement says that a “signed binary number” has one sign bit and the rest of the bits hold the magnitude. This is strictly true for the sign–magnitude format, and the question asks you to evaluate it with that context in mind. Given Data / Assumptions: We are talking about signed integer encodings used in hardware. In sign–magnitude, the most significant bit (MSB) is the sign indicator. In two's complement, the MSB also indicates negativity, but the remaining bits do not simply hold the magnitude; the code is weighted. Concept / Approach: In sign–magnitude, the layout is: sign bit (0 for positive, 1 for negative) + magnitude field (binary of the absolute value). In two's complement, negativity is encoded by inverting and adding 1, which changes the numeric weighting of all bits. Therefore, the literal description “one sign bit + magnitude bits” is accurate for sign–magnitude, not for two's complement. Step-by-Step Solution: Identify the described format: one sign bit, magnitude elsewhere → sign–magnitude.Check if the claim matches sign–magnitude → yes.Acknowledge that other signed systems (two's complement, one's complement) differ, but the claim holds in the stated representation. Verification / Alternative check: Examples: With 8 bits, +5 is 0000 0101; −5 in sign–magnitude is 1000 0101. The magnitude field is unchanged; only the sign bit flips. Why Other Options Are Wrong: “Incorrect” ignores the validity for sign–magnitude. “Applies only to octal numbers” is irrelevant. “Insufficient information” is unnecessary because the stem explicitly frames sign–magnitude. Common Pitfalls: Confusing sign–magnitude with two's complement, where bit patterns are not a simple sign + magnitude. Final Answer: Correct

Question 16

Binary subtraction with borrowing through zeros: When a borrow is needed from a bit position that contains 0, you must borrow from the next more significant position that contains 1; every 0 passed becomes 1 after the borrow chain, and the final pos…

Accepted Answer

Introduction / Context: Borrowing in binary subtraction follows patterns similar to decimal subtraction, but with base 2. Understanding the borrow chain through consecutive zeros is essential for hand calculations and for reasoning about hardware subtractors. Given Data / Assumptions: Base-2 subtraction using standard borrow (no complements method in this explanation). Minuend and subtrahend aligned by bit significance. Borrow propagates from more significant to less significant positions. Concept / Approach: When the current bit of the minuend is 0 and you need to subtract 1 (or a higher sub-bit), you cannot subtract without a borrow. If the immediate higher bit is also 0, you move left until a 1 is found. That 1 becomes 0, and every intermediate 0 becomes 1 because each received a borrow and then passed a borrow to the next lower bit. Step-by-Step Solution: Scan left to find the first 1 above the target position.Change that 1 to 0 and convert all intervening 0s to 1s as the borrow ripples right.Use the borrowed 1 (which represents +2 in that bit position) to complete the subtraction locally. Verification / Alternative check: Example: 10000 − 00001. To subtract at the LSB, you search left until the MSB; it becomes 0, all zeros in between become 1, and the final result is 01111. Why Other Options Are Wrong: “Invalid” contradicts the fundamental base-2 borrowing rule. The octal/BCD qualifiers are irrelevant to binary subtraction mechanics. Common Pitfalls: Forgetting to flip each intermediate 0 to 1 during the borrow chain, which leads to errors in multiple adjacent positions. Final Answer: Valid

Question 17

Two’s complement arithmetic: Using the two’s complement system, we can add numbers of any sign (including like signs) with the same adder hardware and obtain a correct signed result when interpreted in two’s complement.

Accepted Answer

Introduction / Context: Two’s complement is the dominant signed-integer format in processors because a single binary adder can handle both addition and subtraction. The claim is that adding numbers with like signs works correctly in this system. In fact, two’s complement supports addition for both like and unlike signs seamlessly. Given Data / Assumptions: Operands are represented in two’s complement using a fixed width (n bits). We use standard binary addition; overflow is detected by carry into/out of the sign bit mismatch. Results are interpreted in the same width (mod 2^n arithmetic). Concept / Approach: Two’s complement encodes negative x as 2^n − |x|. A single binary adder can add any two n-bit patterns and produce a correct two’s complement result, with overflow indicated when the carries into and out of the MSB differ. Like-sign addition is no exception; the arithmetic is uniform. Step-by-Step Solution: Represent both integers in two’s complement.Perform binary addition; ignore the final carry out of the MSB.Check overflow: if sign of operands is the same and sign of result differs, overflow occurred. Verification / Alternative check: Example with 8 bits: 0010 0101 (+37) + 0000 1011 (+11) = 0011 0000 (+48) — correct. With negatives, 1110 1101 (−19) + 1111 1001 (−7) = 1100 0110 (−58) — correct, no extra hardware. Why Other Options Are Wrong: Limiting correctness to positive operands or to sign–magnitude ignores the key advantage of two’s complement: uniform addition for all signs. Common Pitfalls: Confusing carry-out with overflow; in two’s complement overflow is not the same as a simple carry. Final Answer: Correct

Question 18

End-around carry in one’s complement arithmetic: In one’s complement addition/subtraction, if an end carry is generated beyond the most significant bit, that 1 is added back into the least significant bit. Assess this definition.

Accepted Answer

Introduction / Context: One’s complement is an older signed-number system where negative numbers are formed by inverting all bits. Arithmetic in one’s complement uses the “end-around carry” rule to restore a correct result whenever an addition produces a carry out of the most significant bit. Given Data / Assumptions: Fixed-width one’s complement representation. We perform addition of bit patterns and may apply an end-around carry if one occurs. Subtraction can be implemented as addition of the one’s complement of the subtrahend. Concept / Approach: If an addition creates a carry out of the MSB, that carry represents a wrap-around in modulo arithmetic. In one’s complement, you add that single carry bit back into the least significant bit of the sum to obtain the final, corrected result. This distinguishes it from two’s complement, where the final carry is discarded. Step-by-Step Solution: Add the two one’s complement operands bitwise.If there is a carry out of the MSB, add 1 to the LSB of the tentative sum.Interpret the result again as one’s complement (note the presence of both +0 and −0 encodings). Verification / Alternative check: Example (4-bit): 0101 (+5) + 1010 (−5) = 1111 with no end carry → represents −0; with 0111 (+7) + 0100 (+4) = 1011 and end carry 1 → add to LSB yields 1100 (+11), correct. Why Other Options Are Wrong: “Invalid” contradicts the core rule of one’s complement arithmetic. Two’s complement and BCD follow different rules (carry is discarded in two’s complement, and BCD uses digit-wise corrections). Common Pitfalls: Mixing one’s and two’s complement rules; forgetting the final add-back of the end carry results in an off-by-one error. Final Answer: Valid

Question 19

Half adder vs full adder capability: A full adder adds three one-bit inputs (A, B, and a carry-in), whereas a half adder adds exactly two one-bit inputs with no carry-in. Evaluate the statement that “a half adder adds 1-1/2 bits.”

Accepted Answer

Introduction / Context: Adders are fundamental building blocks in arithmetic logic units. It is crucial to distinguish the functional inputs of a half adder and a full adder to design multi-bit adders properly. Given Data / Assumptions: Half adder inputs: A and B (single bits); outputs: Sum and Carry-out. Full adder inputs: A, B, and Cin; outputs: Sum and Cout. No timing or speed enhancements are implied. Concept / Approach: The “1-1/2 bits” phrase is informal and misleading. A half adder adds exactly two one-bit inputs and produces a two-bit result (Sum and Carry-out). A full adder explicitly incorporates carry-in so that adders can be chained bit by bit to form a ripple-carry adder. Step-by-Step Solution: Define half adder: implements Sum = A XOR B; Cout = A * B.Define full adder: Sum = A XOR B XOR Cin; Cout = majority(A, B, Cin).Show that full adder handles three 1-bit inputs simultaneously; half adder does not accept Cin. Verification / Alternative check: To create multi-bit adders, chain one half adder only at the least significant stage (with Cin = 0), then use full adders for higher bits where Cin is non-zero. Why Other Options Are Wrong: “Correct — 1.5 bits” is not a formal concept. Cascading or propagation delay does not redefine the basic inputs of a half adder. Common Pitfalls: Assuming a half adder can handle incoming carry; attempting to cascade half adders alone will fail for multi-bit addition with carries. Final Answer: Incorrect — a half adder adds two 1-bit inputs (no carry-in).

Question 20

Subtraction terminology: In arithmetic subtraction, the correct operand names are “minuend” for the number being reduced and “subtrahend” for the amount subtracted (not “subend”). Assess this terminology.

Accepted Answer

Introduction / Context: Precise terminology matters in mathematics and digital design documentation. In subtraction, confusing the operand names can lead to misunderstandings when specifying algorithms or verifying arithmetic circuits. Given Data / Assumptions: The operation is subtraction: Minuend − Subtrahend = Difference. We use standard mathematical terminology recognized in textbooks and technical references. The term “subend” is a misspelling/misuse. Concept / Approach: The minuend is the quantity from which another quantity is subtracted. The subtrahend is the quantity being subtracted. These names apply in all radices (decimal, binary, etc.) because they describe roles, not number systems. Step-by-Step Solution: Identify the operation: x − y = z.Map terms: x is the minuend, y is the subtrahend, z is the difference.Confirm usage is independent of number base or implementation method (direct subtraction or complements arithmetic). Verification / Alternative check: Any elementary arithmetic reference will list these terms, and digital design texts retain the same terminology when describing subtractor circuits. Why Other Options Are Wrong: “Incorrect” is wrong because the names given are standard. Limiting to decimal or to a particular subtraction method confuses representation with terminology. Common Pitfalls: Reversing the roles (calling the subtrahend the minuend) or using nonstandard terms can cause errors in specifications and testbenches. Final Answer: Correct

Arithmetic Operations and Circuits Questions