Question 1

Two’s complement addition (8-bit): Add 11110010 and 11110011. First identify each 8-bit number's decimal sign and magnitude, then compute their decimal sum.

Accepted Answer

Introduction / Context: Two’s complement is the dominant signed binary representation used by processors. Mastery involves recognizing negative values, converting between binary and decimal, and performing addition with correct overflow interpretation. Given Data / Assumptions: Word size: 8 bits. Operands: 11110010 and 11110011. Interpretation: two’s complement signed integers. Concept / Approach: For two’s complement: if the MSB is 1, the value is negative and equals the negative of the two’s complement magnitude. To find magnitude: invert bits, add 1. Addition of two’s complement numbers uses ordinary binary addition; discard any carry beyond 8 bits, then interpret the result with sign bit. Step-by-Step Solution: Number A = 11110010 → MSB = 1 → negative. Invert: 00001101; add 1 → 00001110 = 14 → A = –14.Number B = 11110011 → MSB = 1 → negative. Invert: 00001100; add 1 → 00001101 = 13 → B = –13.Sum: –14 + –13 = –27 (decimal).Binary add (optional check): 11110010 + 11110011 = 1 11100101 (9-bit). Discard carry → 11100101. Invert to check magnitude: 00011010; add 1 → 00011011 = 27; MSB 1 → –27. Verification / Alternative check: Decimal arithmetic confirms –27. The sign bit of 11100101 is 1 and magnitude check yields 27, consistent with –27. No signed overflow occurred here because adding two negatives cannot overflow into positive in 8-bit unless magnitude exceeds range, which it does not (range is –128 to +127). Why Other Options Are Wrong: –113 and –114; 227: Magnitudes misread and sum sign incorrect. –27 and –13; 40: First operand’s interpretation wrong; sum inconsistent. –11 and –16; –27: Operand magnitudes misdecoded. Common Pitfalls: Forgetting to invert then add 1 when decoding negatives; mishandling end carry; misinterpreting the sign bit after addition. Final Answer: –14 and –13; –27

Question 2

Compute –11 + (–2) using 8-bit two’s complement. Which 8-bit two’s-complement result is obtained?

Accepted Answer

Introduction / Context: Binary arithmetic with signed numbers relies on two’s complement encoding. This question checks your ability to encode negatives and perform binary addition correctly within a fixed word size (8 bits). Given Data / Assumptions: Operands: –11 and –2. Word length: 8 bits. Two’s complement arithmetic; discard carry out of MSB. Concept / Approach: To represent –N in two’s complement: write N in binary, invert all bits, then add 1. Add using binary rules; the carry beyond bit 7 is dropped. Interpret the final 8 bits as two’s complement. Step-by-Step Solution: +11 = 0000 1011 → invert 1111 0100 → add 1 → 1111 0101 (this is –11).+2 = 0000 0010 → invert 1111 1101 → add 1 → 1111 1110 (this is –2).Add: 1111 0101 + 1111 1110 = 1 1111 0011 (9-bit). Discard carry → 1111 0011.Interpret: MSB = 1 → negative. Magnitude check: invert 0000 1100; add 1 → 0000 1101 = 13 → result = –13, which matches –11 + –2 = –13. Verification / Alternative check: Decimal check: –11 + –2 = –13; result encoding 1111 0011 corresponds to –13 in 8-bit two’s complement. Range –128…+127 supports this result without overflow. Why Other Options Are Wrong: 1110 1101 / 1110 1001 / 1111 1001: These bit patterns decode to other negative values (not –13) and do not match the arithmetic. Common Pitfalls: Not discarding the end carry; forgetting the invert+1 rule; mixing sign-magnitude with two’s complement decoding. Final Answer: 1111 0011

Question 3

4-bit parallel adder design: What is the purpose of fast-carry / look-ahead carry circuitry used in most 4-bit parallel adders?

Accepted Answer

Introduction / Context: Adder speed is often limited by carry propagation. Ripple-carry adders propagate carries sequentially, creating cumulative delay. Look-ahead carry logic anticipates carries in parallel, greatly improving performance in arithmetic units. Given Data / Assumptions: Target: 4-bit parallel adder. Technique: carry look-ahead (fast carry). Goal: compare timing behavior vs. ripple carry. Concept / Approach: Carry look-ahead computes generate (G) and propagate (P) signals for each bit, then forms carries for all stages using combinational logic rather than waiting for serial propagation. This reduces overall adder delay from O(n) to approximately O(log n) levels of logic (for hierarchical designs). Step-by-Step Solution: Define bit signals: G_i = A_i * B_i, P_i = A_i + B_i.Compute carries in parallel: C_1, C_2, C_3, C_4 derived from G/P and C_0.Sum outputs S_i = A_i ⊕ B_i ⊕ C_i determined once carries are known quickly. Verification / Alternative check: Timing analysis shows look-ahead reduces the worst-case chain delay inherent in ripple adders. Empirically, 74xx-series look-ahead generators (e.g., 74182) speed up multi-nibble additions by precomputing carries. Why Other Options Are Wrong: increase ripple delay: Opposite of intent. add a 1 to complemented inputs: Not the function of carry look-ahead. determine sign and magnitude: That is post-addition interpretation, not carry acceleration. Common Pitfalls: Assuming look-ahead changes arithmetic results; it only changes timing. Also confusing propagate vs. generate roles. Final Answer: reduce propagation delay

Question 4

Binary addition practice: Add decimal 26 and 27 in binary and choose the correct binary sum.

Accepted Answer

Introduction / Context: Converting between decimal and binary and then performing binary addition reinforces number-system fluency vital for digital logic, encoding, and low-level software work. Given Data / Assumptions: Operands: 26 and 27 (decimal). Required: binary sum. Concept / Approach: Convert each decimal number to binary, perform column-wise binary addition with carries, and then confirm by reconverting the result back to decimal. Step-by-Step Solution: 26 (decimal) = 16 + 8 + 2 = 11010 (binary).27 (decimal) = 16 + 8 + 2 + 1 = 11011 (binary).Add: 11010 + 11011 = 110101 (binary).Check: 110101 = 32 + 16 + 4 + 1 = 53 (decimal); 26 + 27 = 53 → matches. Verification / Alternative check: Decimal calculation confirms 53. Long addition in binary shows carries from lower bits forming the sixth bit in the result, which is expected for sums exceeding 31. Why Other Options Are Wrong: 111010 (58), 110110 (54), 101011 (43): Do not equal 53; arithmetic mismatch. Common Pitfalls: Dropping a carry when adding the least significant bits; mis-conversion of decimal to binary (especially around the 16 and 8 positions). Final Answer: 110101

Question 5

Binary long division: Divide 1100010 (binary) by 0101 (binary 5). What is the decimal remainder of the division?

Accepted Answer

Introduction / Context: Binary division mirrors decimal long division but uses base-2 arithmetic. Understanding remainders is useful for modulus operations, checksums, and cyclic redundancy computations. Given Data / Assumptions: Dividend: 1100010₂. Divisor: 0101₂ (which equals 5₁₀). Asked: decimal value of the remainder. Concept / Approach: You can either perform binary long division directly or convert to decimal to quickly find the remainder, since modulo is base-independent for exact integer values: remainder(98, 5) = 98 mod 5. Step-by-Step Solution: Convert dividend: 1100010₂ = 64 + 32 + 2 = 98₁₀.Convert divisor: 0101₂ = 5₁₀.Compute remainder: 98 mod 5 = 5*19 = 95; 98 – 95 = 3.Therefore, remainder = 3 (decimal). Verification / Alternative check: Binary long division also yields a remainder of 0011₂, which is 3₁₀. Either path confirms the same result, validating the conversion and arithmetic. Why Other Options Are Wrong: 2, 4, 6: Not equal to 98 mod 5; these would be correct only for different dividends. Common Pitfalls: Misreading the dividend bits (especially leading zeros) or miscalculating place values when converting to decimal. Always double-check binary weights (…32, 16, 8, 4, 2, 1). Final Answer: 3

Question 6

ALU control concept: The selector (control) inputs to an arithmetic-logic unit determine what aspect of its operation?

Accepted Answer

Introduction / Context: An arithmetic-logic unit (ALU) is the computational heart of a processor or digital datapath. Control or selector lines command the ALU to perform specific operations on its inputs, enabling instruction execution and micro-operations. Given Data / Assumptions: We consider a generic multi-function ALU with control lines (e.g., S₀…Sₙ). Inputs A and B are operand words; flags may reflect results. Concept / Approach: ALU selector inputs choose among available functions: addition, subtraction (via two’s complement), increment, decrement, logical AND/OR/XOR/NOT, shifts/rotates (if integrated), etc. They do not select the chip itself, the data source, or the system clock rate; those are managed by other subsystems (decoder, multiplexers, clock generator). Step-by-Step Solution: Identify role of selector lines: choose operation among arithmetic and logic functions.Exclude alternatives: IC selection is via chip select; data word selection via multiplexers; clock frequency via clock circuitry, not ALU selectors.Therefore, the correct mapping is: selector inputs → chosen arithmetic/logic function. Verification / Alternative check: Examine classic ALUs (e.g., 74181). Control bits determine whether the unit performs arithmetic vs. logic operations and which specific function, confirming the principle. Why Other Options Are Wrong: selection of the IC: Handled by chip-select, not ALU function selectors. data word selection: Controlled by multiplexers and register enables. clock frequency: Provided by the system clock, independent of ALU function codes. Common Pitfalls: Confusing ALU function control with instruction decode or bus selection signals; remember the ALU only transforms input data according to these selector codes. Final Answer: arithmetic or logic function

Question 7

Two’s complement subtraction setup: To compute 43 − 15 in binary by addition, which 6-bit two’s-complement code should be added to 43 to represent “minus 15”?

Accepted Answer

Introduction / Context: Digital systems perform subtraction by adding the two’s complement of the subtrahend. Selecting the correct two’s-complement pattern is crucial for correct results and for understanding how ALUs handle subtraction internally. Given Data / Assumptions: Operation: 43 − 15. Assume 6-bit words (sufficient since 43 is 101011₂ and 15 is 001111₂). Task: choose the 6-bit two’s complement of 15 to add to 43. Concept / Approach: For two’s complement: –N = invert(all bits of N) + 1. Represent 15 in 6 bits, form its two’s complement, and identify the correct option. Step-by-Step Solution: 15 (decimal) in 6 bits = 00 1111 → 001111.Invert: 110000.Add 1: 110000 + 000001 = 110001. This is the 6-bit code for –15.Therefore, to compute 43 − 15, add 43 + 110001 (the two’s complement of 15). Verification / Alternative check: Perform the addition: 43 (101011) + 110001 = 1 011100 (ignore carry) = 011100 = 28, which equals 43 − 15, confirming the correctness. Why Other Options Are Wrong: 110000: Missing the +1 step; this is one’s complement of 15, not two’s. 101011 / 011100: These are unrelated values (43 and 28, respectively), not the needed complement. Common Pitfalls: Forgetting to add 1 after inversion; using too few bits so that sign is lost; misreading leading zeros in fixed-width formats. Final Answer: 110001

Question 8

Adder fundamentals: Name the two basic adder building blocks used in digital circuits.

Accepted Answer

Introduction / Context: Adders are foundational to arithmetic units, counters, checksum generators, and digital signal processing blocks. Understanding the elemental adder cells clarifies how wider adders and ALUs are constructed. Given Data / Assumptions: We seek the canonical names of the smallest adder units. System uses binary arithmetic with carry handling. Concept / Approach: A half adder adds two single-bit operands and produces a sum and a carry (no carry-in). A full adder extends this by including a carry-in input, allowing chaining to create multi-bit ripple or look-ahead adders. Parallel adders are assemblies of full adders; they are not a different “basic type.” Step-by-Step Solution: Half adder: inputs A, B; outputs Sum = A ⊕ B, Carry = A * B.Full adder: inputs A, B, Cin; outputs Sum = A ⊕ B ⊕ Cin; Cout = majority(A, B, Cin).Chain N full adders to form an N-bit parallel adder (ripple or with carry acceleration). Verification / Alternative check: Standard logic libraries and textbooks specify these two as primitive adder cells; all larger adders decompose to these functions. Why Other Options Are Wrong: half adder and parallel adder: “Parallel adder” is a composition of full adders, not a primitive. asynchronous and synchronous: Timing classifications, not adder cell types. one’s complement and two’s complement: Number representations, not adder circuit types. Common Pitfalls: Confusing architectural composition (“parallel adder”) with primitive cells; conflating numeric representations with hardware blocks. Final Answer: half adder and full adder

Question 9

Binary multiplication practice When multiplying the decimal numbers 13 × 11 using binary arithmetic (13 = 1101₂ and 11 = 1011₂), what is the third partial product generated during the shift-and-add process?

Accepted Answer

Introduction / Context: This problem checks your understanding of binary multiplication by hand, specifically identifying the intermediate (partial) products that arise when a multiplicand is conditionally shifted and added based on the multiplier bits. Given Data / Assumptions: Multiplicand: 13₁₀ = 1101₂. Multiplier: 11₁₀ = 1011₂ (bits processed from least significant to most significant). Standard shift-and-add binary multiplication procedure. Concept / Approach: For each bit of the multiplier (from LSB to MSB), write a partial product: either the multiplicand left-shifted by the bit position (if that bit is 1) or a row of zeros (if that bit is 0). The “third partial product” corresponds to the third processed bit of the multiplier (bit index 2, counting from 0 at the LSB). Step-by-Step Solution: Write numbers: multiplicand = 1101₂, multiplier = 1011₂.Bit 0 (LSB) of multiplier = 1 → 1st partial product = 1101.Bit 1 of multiplier = 1 → 2nd partial product = 11010 (one left shift).Bit 2 of multiplier = 0 → 3rd partial product = 0000 (all zeros, two-position row).Bit 3 of multiplier = 1 → 4th partial product = 1101000 (three left shifts). Verification / Alternative check: If the third multiplier bit is zero, no contribution occurs at that stage, so the corresponding row must be zeros, confirming the choice. Why Other Options Are Wrong: 100000 / 100001 / 1011: These represent nonzero rows; they would imply a 1 in the third multiplier bit, which is not the case. Common Pitfalls: Counting partial products from the MSB side or forgetting that a 0 multiplier bit yields an all-zero partial product. Final Answer: 0000

Question 10

Two's-complement limits For an 8-bit two's-complement binary number, what is the numerical range represented (inclusive)?

Accepted Answer

Introduction / Context: Understanding the representable range of two's-complement integers is fundamental for overflow checks, embedded systems programming, and digital arithmetic design. Given Data / Assumptions: Word size n = 8 bits. Two's-complement representation with one sign bit. Concept / Approach: The two's-complement range is: minimum = −2^(n−1), maximum = +2^(n−1) − 1. This asymmetry arises because there is only one representation for zero, leaving an extra negative value. Step-by-Step Solution: Compute min: −2^(8−1) = −2^7 = −128.Compute max: +2^(8−1) − 1 = +2^7 − 1 = +127.Therefore, range is −128 to +127 (base 10). Verification / Alternative check: List extreme bit patterns: 10000000₂ = −128; 01111111₂ = +127, confirming the range. Why Other Options Are Wrong: Options showing +128 as representable are incorrect in two's complement; +128 requires 9 bits. Common Pitfalls: Confusing sign-magnitude with two's complement or assuming symmetry about zero. Final Answer: –12810 to +12710

Question 11

Counting single-bit subtraction cases How many distinct basic one-bit binary subtraction operations (A − B, without borrow-in) are possible?

Accepted Answer

Introduction / Context: Binary subtraction at the single-bit level underpins subtractor design and the generation of borrow signals in arithmetic logic units. Given Data / Assumptions: Single-bit operands A and B ∈ {0,1}. No borrow-in (Bin = 0). Outputs: difference bit D and borrow-out Bout. Concept / Approach: With two binary inputs A and B, there are 2 × 2 = 4 input combinations. Each combination yields a defined (D, Bout). Step-by-Step Solution: List cases: (A,B) = (0,0), (0,1), (1,0), (1,1).Compute D,Bout for each: 0−0→D=0,Bout=0; 0−1→D=1,Bout=1; 1−0→D=1,Bout=0; 1−1→D=0,Bout=0.Thus, there are four distinct basic operations. Verification / Alternative check: Truth table of a one-bit subtractor confirms four rows. Why Other Options Are Wrong: 3, 2, 1: underestimate the number of input combinations. Common Pitfalls: Accidentally including borrow-in changes the table size, but the question specifies basic operations without borrow-in. Final Answer: 4

Question 12

Counting subtraction input combinations For one-bit binary subtraction without borrow-in, how many distinct input combinations (A,B) exist?

Accepted Answer

Introduction / Context: Designing a one-bit subtractor begins with enumerating all input combinations. This ensures complete coverage for truth-table-based or Boolean design. Given Data / Assumptions: Inputs A and B are single bits. No borrow-in. Concept / Approach: Two binary inputs yield 2^2 = 4 distinct combinations. Each combination defines the resulting difference and borrow-out. Step-by-Step Solution: Compute total combinations: 2 inputs → 2^2 = 4.Enumerate: (0,0), (0,1), (1,0), (1,1).Hence, there are four basic combinations. Verification / Alternative check: Cross-check with a subtractor truth table; it contains four rows for A,B without borrow-in. Why Other Options Are Wrong: 3, 2, 1: do not account for all A,B permutations. Common Pitfalls: Confusing “operations” with “results” or mixing in borrow-in, which doubles the rows. Final Answer: 4

Question 13

Two half adders can be combined to form a full adder with no additional gates.

Accepted Answer

False

Question 14

A technique to speed parallel addition by eliminating the delay caused by the carry bit propagation is called fast carry, or look-ahead carry.

Accepted Answer

True

Question 15

Signed binary numbers have one bit that represents the sign, with the remaining bits representing the magnitude.

Accepted Answer

True

Question 16

If you borrow from a position that contains a 0, you must borrow from the more significant bit that contains a 1. All 0s up to that point become 1s, and the digit last borrowed from becomes a 0.

Accepted Answer

True

Question 17

Using the two's complement number system we can add numbers with like signs and obtain the correct result.

Accepted Answer

False

Question 18

End around carry is an operation in 1's complement subtraction where a 1 is added to the sum of the 1's complement of both numbers.

Accepted Answer

False

Question 19

A full adder adds three bits, a half adder adds 1-1/2 bits.

Accepted Answer

False

Question 20

The operands in a subtraction operation are the subend and the minuend.

Accepted Answer

False

Arithmetic Operations and Circuits Questions