Master Reset (MR) on 4-bit binary counters — behavior and usage Select the statement that best describes how the Master Reset inputs (MR1 and MR2) work on typical 4-bit binary counters (e.g., TTL/CMOS families).

Introduction / Context:
The Master Reset (MR) inputs on standard 4-bit binary counters (such as 74xx90/93 asynchronous types and 74xx16x synchronous types) provide an immediate way to force the counter outputs to a known state. Knowing the polarity and effect of MR is essential for designing reliable power-on initialization and for clearing counters during operation.

Given Data / Assumptions:

• Two reset inputs labeled MR1 and MR2 are present.
• Typical counters require both MR inputs to be asserted simultaneously.
• Unless otherwise specified, MR is asynchronous and active-HIGH.

Concept / Approach:
In many TTL/CMOS counter families, Master Reset is implemented as an asynchronous clear that overrides counting. The device datasheets commonly specify that MR1 and MR2 must both be HIGH to activate reset. When asserted, all Q outputs go to 0 and the internal counting chain is cleared immediately, independent of the clock. For normal counting, both MR inputs must be held LOW (inactive).

Step-by-Step Solution:

Verification / Alternative check:
Check a standard counter truth table. You will find entries indicating that when MR inputs are HIGH simultaneously, Q outputs immediately become 0000 and counting halts. When MR returns LOW, counting resumes from 0000 on subsequent clock pulses.

Why Other Options Are Wrong:

• Reset to one: typical MR clears to 0000, not 1111.
• Synchronous reset: most MR implementations are asynchronous; synchronous clears use different pins/control logic.
• “To enable count mode, MR must be LOW”: partially true as a condition, but it does not describe the use; the key behavior is that both HIGH reset to zero.
• Preset via MR: presetting uses dedicated load inputs, not MR.

Common Pitfalls:

• Confusing asynchronous MR with synchronous clear or parallel load control lines.
• Forgetting that some families may use active-LOW clears; always confirm datasheets.

Final Answer:
When MR1 and MR2 are both HIGH, all Qs will be reset to zero.