Ripple (asynchronous) MOD-16 counter — output frequencies per stage A 22 MHz clock drives a MOD-16 binary ripple counter (4 cascaded divide-by-2 stages). What are the output frequencies Q1 through Q4?

Introduction / Context:
A ripple (asynchronous) binary counter is a cascade of divide-by-2 stages. Each flip-flop output frequency is half that of its driving input. Quickly determining the output frequencies is vital when designing frequency dividers, timing chains, and prescalers in digital and mixed-signal systems.

Given Data / Assumptions:

• Input clock fin = 22 MHz.
• MOD-16 counter implemented by 4 toggle stages (divide-by-2 each).
• Outputs labeled Q1 (first stage) through Q4 (fourth stage).

Concept / Approach:
Each stage divides by 2: fQn = fin / 2^n where n is the stage number (1..4). The total modulus is 2^4 = 16, hence MOD-16. Compute successively to avoid mistakes in powers of two and units.

Step-by-Step Solution:

Verification / Alternative check:
Confirm modulus: Q4 period equals 16 input cycles. 22 MHz / 16 = 1.375 MHz, matching the final value. A quick binary check: every stage halves the frequency—no exceptions in a clean ripple chain.

Why Other Options Are Wrong:

• Options with unchanged frequencies (all 22 or all 11 MHz) ignore the divide-by-2 nature.
• Any set not following exact halving at each stage is incorrect.
• The 0.6875 MHz value corresponds to a fifth division (not present here).

Common Pitfalls:

• Mixing up stage numbering or forgetting that Q1 is the first divider output.
• Arithmetic slips when halving odd MHz values; keep one extra decimal place if needed.

Final Answer:
Q1 = 11 MHz, Q2 = 5.5 MHz, Q3 = 2.75 MHz, Q4 = 1.375 MHz