RS flip-flop behavior (set–reset latch): Assume an RS flip-flop with both inputs initially at 0 (R = 0 and S = 0, stable hold condition) and the output Q starting at 0. If a momentary 1 (a brief high pulse) is applied to the S input while R remains 0, what happens to Q once S returns to 0?

Introduction / Context:
This question tests understanding of the fundamental behavior of an RS (Set–Reset) flip-flop, also called an SR latch. Knowing how Q responds to brief set or reset pulses is crucial for designing debouncers, edge detectors, and simple memory elements in digital electronics.

Given Data / Assumptions:

• Initial condition: R = 0, S = 0 (the hold state), and Q = 0.
• A momentary 1 (short pulse) is applied to S while R remains 0.
• After the pulse, S returns to 0 (so S = 0 and R = 0 again).
• We consider a typical active-high RS latch with cross-coupled gates (NOR or NAND as appropriate for active levels).

Concept / Approach:
In an active-high RS latch, asserting S = 1 drives the latch into the set state. Once set, the internal cross-coupling provides positive feedback that maintains Q = 1 even after S returns to 0, as long as R stays at 0. This is the essence of memory in a latch: it holds the last commanded state until another valid command (reset) arrives.

Step-by-Step Solution:
Start: R = 0, S = 0, Q = 0 → stable hold at Q = 0.Apply a brief set pulse: S = 1, R = 0 → the latch sets, forcing Q = 1.Remove the pulse: S returns to 0 while R = 0 → the latch is back in the hold state but now holds Q = 1.Conclusion: Q flips from 0 to 1 and remains 1 until a reset (R = 1) occurs.

Verification / Alternative check:
Truth behavior of a NOR-latch (active-high): S = 1, R = 0 → Q = 1 (set). Returning both to 0 keeps the last state. Only R = 1 will reset Q to 0. This aligns with standard timing diagrams of SR latches.

Why Other Options Are Wrong:
(a) A latch does not free-run; it is level-sensitive storage. (b) Returning S to 0 does not undo the set; only R = 1 resets. (c) R = 0 does not force Q low; it merely refrains from resetting. (e) Metastability is associated with illegal inputs (S = R = 1) or setup/hold violations, not a clean S pulse.

Common Pitfalls:
Confusing hold (S = 0, R = 0) with reset; thinking that S must stay 1 to keep Q = 1; or mixing NOR-latch (active-high) with NAND-latch polarity. Always check active levels and the last commanded state.

Final Answer:
Q flips from 0 to 1 and remains latched at 1 after S returns to 0.