RAM interface signals (read/write addressing): Complete the requirement: “Random-access memory (RAM) devices must have an address input, in addition to the data-in input, to select which location is written.” Evaluate the correctness of this requirement.

Introduction / Context:
Writing to memory is fundamentally a two-part operation: you must indicate what data you are providing and where to store it. The “where” is specified through the address input(s). This question ensures that learners associate write operations with both data and addressing, rather than thinking of RAM as a simple latch without selection.

Given Data / Assumptions:

• The device is a parallel RAM (static or dynamic) with random access.
• Control pins (e.g., Chip Select, Write Enable, Output Enable) exist in addition to address and data signals.
• We are not discussing shift-register memories or serial EEPROM streams where addressing may be embedded in a command sequence.

Concept / Approach:
In RAM, each storage cell is reached via an address. For SRAM, the address directly selects the word line; for DRAM, row/column multiplexing (A0..An via RAS/CAS) selects a single bit/word. During a write cycle, the memory captures the value on the data-in line(s) into the location specified by the active address while control signals (CS/OE/WE or RAS/CAS/W) define the operation. Thus, an address input is essential alongside data-in for any meaningful write.

Step-by-Step Solution:

Verification / Alternative check:
Examine any SRAM/DRAM timing diagram: the address is valid (or latched) during the write window while WE is asserted; the data lines are sampled into the selected cell/word.

Why Other Options Are Wrong:

Common Pitfalls:
Confusing “random access” with “no address needed,” or thinking Chip Select alone chooses a unique location.

Final Answer:
Correct