Parallel RC circuits and phase behavior with frequency Evaluate the statement: “If the excitation frequency increases in a parallel RC circuit, the phase angle between the source voltage and the total current decreases.” State whether this claim is valid and briefly justify your choice.

Introduction / Context:
In alternating-current (AC) circuit analysis, understanding how phase angle varies with frequency is fundamental for filters, sensor interfaces, and power systems. A parallel RC network exhibits a frequency-dependent current lead relative to the applied voltage. This question tests whether you know the direction of that change as frequency increases.

Given Data / Assumptions:

• Topology: parallel RC circuit (a resistor R in parallel with a capacitor C).
• Source: sinusoidal voltage excitation.
• Ideal components (ignore capacitor ESR and wiring parasitics unless noted).
• Phase angle referenced between source voltage and total line current.

Concept / Approach:
The parallel RC is best analyzed using admittance Y. The total admittance is Y = G + jB where G = 1/R and B = ωC. The total current phasor leads the voltage by angle θ such that tan(θ) = B / G = (ωC) / (1/R) = ωCR. Because B increases linearly with frequency, the current’s lead angle increases with frequency.

Step-by-Step Solution:

Verification / Alternative check:
At very low frequency (ω → 0), B → 0 and θ → 0°, so the circuit behaves resistively. At very high frequency, B ≫ G and θ approaches 90°, dominated by capacitive current. This confirms that θ increases with frequency, not decreases.

Why Other Options Are Wrong:

Common Pitfalls:
Confusing series vs. parallel behavior; mixing voltage-lead with current-lead language; assuming capacitor current behavior from series circuits applies identically to parallel circuits.

Final Answer:
Incorrect