Dual-gate D-MOSFETs often exhibit a lower overall input capacitance. What is the usual connection of the two gates that leads to this reduced effective capacitance?

Introduction / Context:
Dual-gate MOSFETs are popular in RF front-ends and mixers because they allow gain control and improved isolation. A practical benefit is reduced effective input capacitance seen by the preceding stage, which helps extend bandwidth and ease matching.

Given Data / Assumptions:

• Device: dual-gate depletion MOSFET (D-MOSFET).
• Question: why the overall input capacitance is lower.
• Key concept: series combination of gate capacitances.

Concept / Approach:
When two capacitances are connected in series, the net capacitance is lower than either individual capacitance. In dual-gate MOSFETs, the two gate structures can behave like series-connected capacitors from the input to the channel, thereby reducing the effective input capacitance and improving high-frequency performance.

Step-by-Step Solution:
Model each gate with its gate-to-channel capacitance.Recognize that the cascading of two gates places these capacitances effectively in series from the RF input’s perspective.Series combination yields C_total less than either individual C, lowering input loading.

Verification / Alternative check:
RF small-signal models reflect reduced Cin and improved reverse isolation (feedback capacitance partitioning), consistent with measured S-parameters of dual-gate devices.

Why Other Options Are Wrong:

• In parallel: Would increase, not decrease, effective input capacitance.
• With separate insulation / with separate inputs: True physical attributes but not the electrical reason for lower effective capacitance.

Common Pitfalls:

• Assuming lower capacitance is due only to process differences; topology (series effect) is the key factor.
• Ignoring how reduced Cin affects input matching at high frequencies.

Final Answer:
in series