Enhancement-mode MOSFET (E-MOSFET) at zero gate bias: When the gate-to-source voltage VGS = 0 V for an E-MOSFET, what is the drain current?

Introduction / Context:
Enhancement-mode MOSFETs are normally-OFF devices. Unlike depletion-mode devices (JFETs or D-MOSFETs), an E-MOSFET requires a gate voltage above a threshold to induce a conducting channel. Knowing this default state is crucial for switch design, power stages, and fail-safe behavior.

Given Data / Assumptions:

• Ideal n-channel E-MOSFET (the same logic applies for p-channel with polarities reversed).
• VGS = 0 V relative to the source.
• Leakage currents neglected for the ideal statement.

Concept / Approach:

With VGS = 0 V, no inversion channel exists between source and drain, so the device is OFF and conducts only negligible leakage. Once VGS exceeds the threshold voltage (Vth), an inversion layer forms, allowing significant current to flow for adequate VDS.

Step-by-Step Solution:

Verification / Alternative check:

Datasheets show ID(off) (leakage) in the microamp or nanoamp range at VGS = 0; switching circuits rely on this normally-OFF property for safety and control.

Why Other Options Are Wrong:

• At saturation/widening the channel: requires VGS above threshold.
• IDSS: JFET parameter, not applicable to E-MOSFETs.
• Leakage only (option e) is technically true in practice, but the standard textbook answer for ideal behavior is “zero.”

Common Pitfalls:

• Confusing depletion-mode and enhancement-mode FET behavior.
• Assuming MOSFETs always pass current with any VDS; gate control is essential.

Final Answer:

zero