Difficulty: Easy
Correct Answer: S = 0, R = 0
Explanation:
Introduction / Context: The simplest memory element in digital logic is the S-R latch constructed from two cross-coupled NOR gates. Knowing which input combinations set, reset, or hold the state is essential for analyzing asynchronous hazards and for building higher-level sequential elements.
Given Data / Assumptions:
Concept / Approach: For a NOR-latch, active-HIGH S forces Q = 1 (set), and active-HIGH R forces Q = 0 (reset). When both S and R are LOW, neither gate’s direct input asserts, so feedback maintains the existing state. If both S and R are HIGH simultaneously, both outputs are driven LOW, producing an invalid/forbidden condition because Q and Q’ are no longer complements after inputs return LOW.
Step-by-Step Solution:
S=1, R=0 → Q is driven HIGH (set).S=0, R=1 → Q is driven LOW (reset).S=0, R=0 → no direct drive; outputs stay latched (HOLD).S=1, R=1 → invalid state (both outputs LOW for NOR implementation).Verification / Alternative check:
Trace gate equations: Q = NOR(R, Q’), Q’ = NOR(S, Q). With S=R=0, each gate output depends only on the feedback term, preserving state.Why Other Options Are Wrong:
S=1, R=1: forbidden/invalid for NOR latch.S=1, R=0 and S=0, R=1: these force set or reset, not hold.Common Pitfalls:
Mixing NOR and NAND latch conventions (active-LOW vs. active-HIGH control).Forgetting that S=R=1 is forbidden for NOR latches.Final Answer:
S = 0, R = 0
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