Gated S–R flip-flop (enable-controlled) — condition for CLEAR output A gated S–R flip-flop goes to the CLEAR state under which input condition?

Introduction / Context:
Gated S–R flip-flops include an enable (EN) input that qualifies when the S and R inputs may affect the internal latch. Understanding how EN gates the set/reset commands is essential for designing control logic.

Given Data / Assumptions:

• Active-high enable: S and R are effective only when EN = 1.
• Active-high S sets Q = 1; active-high R resets (clears) Q = 0.
• When EN = 0, the device ignores S and R and holds its state.

Concept / Approach:
To force CLEAR (Q = 0), the reset input must be asserted while the gate allows it to pass to the latch. Thus R must be high and EN must be high at the same time. S must be low to avoid the invalid or conflicting input combination.

Step-by-Step Solution:
Ensure EN = 1 so inputs can act on the latch.Apply R = 1 and S = 0 to command a reset (clear).Latch drives Q → 0 and Q̄ → 1, entering CLEAR.Maintain or release inputs as required; with EN low, state is held.

Verification / Alternative check:
Examine the truth table of a gated S–R latch: with EN = 1, S = 0, R = 1 leads to Q(next) = 0. With EN = 0, inputs have no effect.

Why Other Options Are Wrong:
Option A sets, not clears. Option C has EN low, so no action occurs. Option D also has EN low, preventing state change.

Common Pitfalls:
Forgetting EN polarity; asserting both S and R simultaneously; confusing NAND- and NOR-based latch polarities.

Final Answer:
S is LOW; R is HIGH; EN is HIGH