In a microprocessor system, what is a non maskable interrupt (NMI)?

Introduction / Context:
Alongside maskable interrupts, many microprocessor architectures provide at least one non maskable interrupt input, often labeled NMI. This signal is reserved for very important events such as serious hardware failures, watchdog timer expirations or emergency conditions that must be handled immediately. Knowing what makes an interrupt non maskable and how it differs from regular interrupts is fundamental in hardware and embedded system design.

Given Data / Assumptions:

We are considering microprocessors that support both maskable and non maskable interrupts.
Maskable interrupts can be disabled by clearing interrupt enable flags.
Non maskable interrupts are intended for critical conditions that require immediate attention.
The question asks what NMI means conceptually, not for specific pin names on a particular chip.

Concept / Approach:
A non maskable interrupt is an interrupt input that bypasses the normal interrupt enable or mask logic. It typically has high priority and will be recognised by the processor even if maskable interrupts have been disabled by software. Because it cannot be easily ignored, NMI is reserved for critical conditions where the system must attempt to execute an emergency service routine, for example to log an error, place the system in a safe state or reset. However, some architectures still allow NMI to be inhibited during reset or in very specific modes.

Step-by-Step Solution:
Step 1: Recall that maskable interrupts are controlled by software using interrupt enable bits. When disabled, the processor ignores those signals. Step 2: Recognise that non maskable interrupts must still be recognised even when maskable interrupts are disabled, or else they would not provide the necessary guarantee for critical events. Step 3: Understand that because NMI bypasses normal masking, it is assigned to high priority events like memory parity errors or watchdog timeouts. Step 4: Conclude that a non maskable interrupt is a high priority interrupt which cannot be disabled using the standard masking mechanism and is reserved for serious events.

Verification / Alternative check:
On many classic microprocessors such as the Intel 8086, there is a dedicated NMI pin. Documentation explains that this input causes an immediate interrupt sequence that is not affected by the state of the interrupt enable flag. Operating systems and firmware often connect NMI to serious error detection logic or to special keys on the keyboard for emergency debugging. This behaviour illustrates that NMI is non maskable in practice.

Why Other Options Are Wrong:
An interrupt that is always generated by software refers to software interrupts or traps, which can be maskable or non maskable depending on design, but this does not define NMI.
An interrupt that is permanently disabled and can never be serviced would be useless; real NMIs are specifically designed to be serviced when triggered.
An interrupt used only for debugging and with lower priority than all others contradicts the high priority and critical nature of NMI.

Common Pitfalls:
One pitfall is to treat NMI like any other interrupt and attempt to mask it using normal enable bits, which does not work. Another is to allocate NMI to non critical functions, wasting a very valuable system resource. Designers should carefully reserve NMI for truly urgent conditions and keep its interrupt service routine as simple and reliable as possible.

Final Answer:
A non maskable interrupt is a high priority interrupt that cannot be disabled by normal interrupt masking and is reserved for critical events.