You have a combinational logic circuit placed between two edge triggered registers driven by the same clock. If the propagation delay of the combinational circuit is greater than the clock period, what design action should you take to make the circuit meet timing?

Introduction / Context:
Synchronous digital design relies on the assumption that signals launched from one register will propagate through combinational logic and arrive at the next register before the next active clock edge. The maximum delay of the combinational path between registers determines the minimum possible clock period. When the combinational delay exceeds the chosen clock period, setup time violations occur and the circuit will not operate reliably at the desired frequency. This question asks what architectural action a designer should take to correct such a situation.

Given Data / Assumptions:

We have a synchronous system with edge triggered registers driven by a common clock.
Between two registers there is a combinational circuit with a known propagation delay.
The delay of this combinational block is greater than the clock period, causing timing violations.
The functional behaviour of the circuit must be preserved while adjusting the design for timing.
We are free to modify the internal staging of the pipeline but not to change the overall external behaviour.

Concept / Approach:
When a combinational path is too slow for a given clock period, one of the standard techniques in synchronous design is pipelining. Pipelining involves inserting additional registers along the critical path, splitting the original combinational block into two or more shorter stages. Each shorter path then has a reduced propagation delay that can meet the clock period. This may increase the number of clock cycles of latency from input to output but allows the circuit to run at a higher frequency. Other strategies like simply ignoring timing or reducing supply voltage are incorrect and unsafe.

Step-by-Step Solution:
Step 1: Identify the longest combinational path between the two registers, often called the critical path. Its delay currently exceeds the allowed clock period. Step 2: Understand that for correct operation, the clock period must be greater than or equal to the sum of the clock to Q delay of the launching register, the combinational path delay and the setup time of the receiving register. Step 3: Recognise that attempting to run the circuit faster than this limit causes setup time violations, which lead to incorrect or unstable data being captured. Step 4: Apply the pipelining technique by inserting one or more additional edge triggered registers into the long combinational path. This divides the path into multiple stages, each with a shorter propagation delay. Step 5: After inserting pipeline registers, recalculate the delays of each stage to ensure that each stage's logic delay plus register overhead fits within the chosen clock period.

Verification / Alternative check:
Consider a combinational path with a delay of 20 nanoseconds, and a clock period of 10 nanoseconds. The path cannot meet timing in a single stage. If you insert a register roughly in the middle of the logic and rearrange gates so that each stage has about 10 nanoseconds of delay, the circuit can then operate at a 10 nanosecond clock period, assuming clock to Q and setup overheads are also within budget. This example illustrates how pipelining resolves the timing violation by increasing latency but preserving throughput.

Why Other Options Are Wrong:
Ignoring the timing violation is unsafe because the registers do not adapt to slower paths; instead, they will capture incorrect data, causing functional errors or metastability.
Reducing the supply voltage generally makes gates slower, not faster, so it will worsen the timing problem rather than solving it, and can compromise noise margins.
Randomly reordering gates without changing the depth of the logic does not reduce the overall critical path delay; the path must be structurally shortened or split with registers.

Common Pitfalls:
Designers sometimes first try to fix timing by minor gate level changes or by tightening synthesis constraints without considering architectural changes. While small optimisations can help, they may not be enough when the required clock frequency is significantly higher than what a single stage can support. Another pitfall is to pipeline the design without carefully adjusting control logic and protocols, leading to misaligned data and control signals. Proper pipelining requires both timing analysis and functional verification.

Final Answer:
To make the circuit meet timing, you should insert one or more additional pipeline registers to split the combinational path into shorter stages that each meet the clock period.