Match digital building blocks to their typical functions: (A) Shift register, (B) Counter, (C) Decoder — with: (1) Frequency division, (2) Addressing in memory chips, (3) Serial-to-parallel data conversion.

Introduction / Context:
Basic digital modules recur across systems, each solving a canonical task. Recognizing their “textbook” roles helps you design datapaths and control logic efficiently.

Given Data / Assumptions:

• (A) Shift register
• (B) Counter
• (C) Decoder
• Functions: (1) frequency division, (2) memory addressing/line selection, (3) serial-to-parallel conversion

Concept / Approach:

Shift registers reorder bits in time and space; with appropriate taps they convert serial streams to parallel words. Counters advance through states on clock edges; the rollover pattern divides the input clock frequency by an integer. Decoders map n input lines to 2^n mutually exclusive outputs, widely used to select memory rows/columns or I/O devices.

Step-by-Step Solution:

Verification / Alternative check:

74xx/40xx families: 74HC595 (shift), 74HC4040 (counter), 74HC138 (decoder) align with these roles; timing diagrams confirm behavior.

Why Other Options Are Wrong:

Swapping decoder and counter confuses selection logic with time-sequence counting; assigning serial-to-parallel to counters misstates function.

Common Pitfalls:

Overlooking that shift registers can also perform parallel-to-serial (PISO) and simple delay; assuming all frequency division requires PLLs (counters suffice for integer division).

Final Answer:

A-3, B-1, C-2