CMOS low-power mechanism CMOS logic achieves low static power consumption primarily because its gates are built from:

Introduction / Context:
One hallmark of CMOS is extremely low dc power draw in the steady state. This question probes the structural reason behind that characteristic.

Given Data / Assumptions:

• CMOS gates employ both p-channel and n-channel MOSFETs.
• Positive logic convention with supply VDD and ground.
• Focus on static (not switching) power.

Concept / Approach:
In a CMOS inverter, for a logic 1 input, the pMOS is OFF and the nMOS is ON; for a logic 0 input, the pMOS is ON and the nMOS is OFF. In either stable state, there is (ideally) no direct conduction path from VDD to ground, so static current is near zero. The same complementary arrangement extends to complex CMOS logic networks.

Step-by-Step Solution:
Identify complementary structure: pMOS pull-up network + nMOS pull-down network.Check static states: exactly one network conducts to the output; the other is open.Conduction from VDD to ground is blocked in dc steady state.Therefore, low power is due to the use of complementary transistor pairs.

Verification / Alternative check:
Measure current of a CMOS inverter held at logic 0 or 1; static supply current is dominated by leakage, orders of magnitude smaller than bipolar TTL static current.

Why Other Options Are Wrong:
Connecting pads/DIP packages/SSI: packaging or scale does not dictate intrinsic gate power; transistor-level topology does.

Common Pitfalls:
Ignoring dynamic power which rises with frequency and load capacitance: P_dynamic ≈ C_load * VDD^2 * f_switch.

Final Answer:
complementary pairs