Propagation delay naming — identifying the two standard times A logic signal incurs delay when passing through a gate or circuit. What are the two standard propagation delay terms used to specify LOW-to-HIGH and HIGH-to-LOW transitions?

Introduction / Context:
Every logic device has finite speed. Datasheets document propagation delays for both transition directions. Engineers must use these values for timing closure, clock budgeting, and ensuring setup/hold margins are met in synchronous systems.

Given Data / Assumptions:

• Standard notation uses tPLH for the time from an input change to an output transition from LOW to HIGH.
• Standard notation uses tPHL for the time from an input change to an output transition from HIGH to LOW.
• Thresholds are measured at consistent reference levels (for example, 50% points in CMOS families, or defined VIH/VIL thresholds).

Concept / Approach:

Notation tP denotes “propagation,” followed by the transition direction of the output. Thus tPLH is propagation delay to a rising output and tPHL is propagation delay to a falling output. These parameters are often different due to device asymmetry and output structure (totem-pole vs open-collector).

Step-by-Step Solution:

Verification / Alternative check:

Check any standard family datasheet (TTL/HC/HCT/AC): timing tables show tPLH and tPHL explicitly for every gate.

Why Other Options Are Wrong:

Other letter sequences are nonstandard or reversed; they do not correspond to datasheet conventions.

Common Pitfalls:

Confusing input-to-output vs output rise/fall times; rise/fall (tr/tf) describe edge steepness, not input-to-output delay.

Final Answer:

tPLH and tPHL.