Address bus sizing – 512 × 8 organization from 4096 total bits How many address lines are required for a 4096-bit memory organized as 512 words × 8 bits per word?

Introduction / Context:
Address line count is a fundamental design decision when interfacing memories. It depends on the number of addressable words (depth), not the number of bits per word (width).

Given Data / Assumptions:

• Total memory: 4096 bits.
• Organization: 512 × 8 → depth = 512 words, width = 8 bits.
• Each unique address selects one of the 512 words.

Concept / Approach:
The required number of address lines A satisfies 2^A = number of addressable words. Here, words = 512. Since 512 = 2^9, we need 9 binary address lines. Width (8 bits) determines data bus size, not address count.

Step-by-Step Solution:

Verification / Alternative check:
Recall powers of two: 2^8 = 256, 2^9 = 512. Hence A = 9 is minimal and sufficient.

Why Other Options Are Wrong:

• 2, 4, 8: 2^2 = 4, 2^4 = 16, 2^8 = 256, all too small for 512 addresses.

Common Pitfalls:

• Multiplying by width when sizing address lines; address count depends only on depth.

Final Answer:
9