Timing definitions — identify the interval immediately following the active clock transition: In flip-flop timing, the “setup” interval occurs before the sampling edge. What is the name of the critical interval immediately after that active clock transition during which the input must remain stable?

Introduction / Context:
Correctly applying setup and hold time constraints is essential to reliable synchronous design. Violations cause metastability, unpredictable outputs, or intermittent bugs that are hard to reproduce. Designers must clearly distinguish which time window applies before and which applies after the active clock edge.

Given Data / Assumptions:

• We speak about edge-triggered flip-flops sampling data at the active edge.
• Setup time (tsu): minimum time that input must be stable before the edge.
• Hold time (th): minimum time that input must remain stable after the edge.

Concept / Approach:
The data presented to a flip-flop must meet both constraints to ensure correct latching. While “setup time” protects the sampling action leading into the edge, “hold time” ensures that the sampling latch does not see the input change too soon after the edge when internal transients are still resolving.

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