Frequency counter timing window: In a basic digital frequency counter, the range-select input determines the length of time that the ________ is enabled to count input cycles.

Introduction / Context:
A frequency counter measures frequency by counting input pulses during a precisely defined gate time. The choice of gate time (for example, 0.1 s, 1 s, or 10 s) trades off measurement resolution against update rate. The range-select control typically chooses this gate time and thus how long the main counting stage is enabled.

Given Data / Assumptions:

• The design includes a pulse gate timed by a reference clock.
• A BCD counter accumulates pulses while the gate is open.
• A display register latches the result after counting stops.

Concept / Approach:
When the gate is enabled, the primary counter increments for each input pulse. After the selected interval elapses, the gate closes, the BCD count is transferred to the display register, and the system resets for the next measurement. The “range select” therefore adjusts the timing that directly affects the counter’s enable window, not merely the display behavior or a test signal source.

Step-by-Step Solution:

Verification / Alternative check:
Simulations show that doubling the gate time doubles the count value for a fixed input frequency, verifying that the BCD counter’s enabled duration determines the measured value.

Why Other Options Are Wrong:

• Display register: Holds or shows the result; it does not define the timing window.
• Frequency prescaler: Optional front-end divider; range select can choose gate time independently of prescaling.
• Signal generator: Not part of a measurement path; used for testing.
• Gate oscillator: Not a standard block name here; the enabling affects the counter.

Common Pitfalls:
Confusing display latch timing with counting duration; assuming prescaler ratios alone define the measurement range; forgetting to reset the counter at the end of the gate.

Final Answer:
BCD counter