Bus contention prevention — which block ensures only one IC drives the bus at a time? In a shared-bus microprocessor system, what logic block guarantees that only the selected device is enabled, preventing two ICs from simultaneously writing different data onto the same bus?

Introduction / Context:
Bus conflicts occur when more than one device drives a shared bus line concurrently, potentially causing excessive current and corrupted data. Proper chip-select (CS) logic ensures that, for any address, at most one device has its outputs enabled. Understanding the role of the address decoder is fundamental to robust memory and I/O mapping.

Given Data / Assumptions:

• Multiple memory and I/O devices share an 8- or 16-bit data bus.
• Each device has an enable/chip-select input.
• The system uses non-overlapping address ranges for each device.

Concept / Approach:
An address decoder interprets high-order address lines (and sometimes control lines like IO/M) to produce one-hot chip-select signals. Only the addressed device's CS is asserted, so only that device's output drivers are enabled. All others remain in high-impedance, eliminating contention. The control bus provides strobes (RD/WR), but without correct decoding, multiple devices could respond simultaneously.

Step-by-Step Solution:

Verification / Alternative check:
Memory maps and schematics show decoders (e.g., 74HC138, PAL/GAL) generating CS lines; logic truth tables demonstrate mutual exclusivity.

Why Other Options Are Wrong:

• Control bus: carries strobes but does not select a single device by address.
• Control instructions: software constructs; hardware-level contention prevention is via decoding.
• CPU: issues addresses but does not inherently provide device-specific CS signals.
• Tri-state buffer without CS: offers high-Z capability, but without decoding it could still be enabled simultaneously.

Common Pitfalls:

• Overlapping decode ranges that cause multiple CS signals to assert; always verify decode equations.

Final Answer:
address decoder