Constructing an S–R flip-flop from basic gates A basic S–R flip-flop can be realized by cross-coupling which types of logic gates?

Introduction / Context:Flip-flops are fundamental memory elements. The simplest form, the S–R latch, is constructed by cross-coupling two logic gates. Recognizing which gate families support this is essential for understanding how memory and feedback are implemented in digital circuits.

Given Data / Assumptions:

• Level-sensitive S–R latch implementation.
• Cross-coupled feedback provides storage.
• Ideal logic levels (no hazards considered here).

Concept / Approach:

Because NAND and NOR gates are universal, cross-coupling them with appropriate input conventions yields an S–R latch. NOR-based latches treat logic HIGH as the active Set/Reset, whereas NAND-based latches treat logic LOW as the active inputs. In both cases, one specific input combination is forbidden (invalid), but normal set, reset, and hold actions are obtained otherwise.

Step-by-Step Explanation:

Verification / Alternative check:

Truth tables for NAND- and NOR-based S–R latches match the expected set, reset, and hold functions when valid inputs are applied.

Why Other Options Are Wrong:

• AND/OR (a, d, e) cannot, by themselves, provide the needed inversion and feedback polarity for a robust S–R latch.
• XOR/XNOR (b) are not used for basic S–R latch construction.

Common Pitfalls:

• Mixing the active levels of inputs between NAND and NOR versions.
• Forgetting the forbidden input case for each version.

Final Answer:

NOR or NAND gates