Why S–R latches stay latched Latches built with NOR or NAND gates tend to hold their state primarily because of which circuit feature?

Introduction / Context:
A latch stores one bit of information by using positive feedback. In basic digital electronics, cross-coupling two gates creates a self-reinforcing loop that prefers either of two states, thereby providing memory. This question targets the core reason the latch holds its state without continuous input drive.

Given Data / Assumptions:

• Standard S–R latch using NOR or NAND gates.
• No clocking; level-sensitive behavior.
• Ideal logic levels assumed.

Concept / Approach:

The essence of memory here is regenerative feedback—each gate’s output feeds the other’s input. Once a state is reached, the feedback biases the partner gate such that the state is reinforced. This cross coupling is what makes a latch a storage element rather than a simple combinational gate chain.

Step-by-Step Explanation:

Verification / Alternative check:

SPICE or logic simulations show that after the inputs return to their inactive levels, the outputs remain latched. Introducing the opposite valid input flips and then re-latches the state.

Why Other Options Are Wrong:

• Asynchronous operation (a) describes timing, not the storage mechanism.
• Low input voltages (b) and gate impedance (c) are incidental electrical details, not the reason for memory.
• Schmitt-trigger inputs (e) add hysteresis/noise immunity but are not necessary for basic latching.

Common Pitfalls:

• Confusing cross coupling with clock gating; latches can be gated, but storage still comes from feedback.
• Overlooking the forbidden input condition that breaks complementarity.

Final Answer:

cross coupling