Gated D-type latch/flip-flop behavior Which statement correctly describes a gated D-type device when the Enable (or gate) input is active?

Introduction / Context:
D-type storage elements come in two common forms: level-sensitive gated latches and edge-triggered flip-flops. When discussing a gated D-type device, the hallmark behavior is that the output Q follows the input D while the Enable (gate) input is active, and then holds the last value when the Enable is inactive.

Given Data / Assumptions:

• Enable-controlled D-type device (level sensitive), not an edge-triggered version.
• Valid logic levels and proper setup/hold with respect to the Enable signal.
• Complementary output Q̄ exists but is not the primary focus.

Concept / Approach:

A gated D latch is transparent when enabled: Q = D. When the Enable goes inactive, Q is latched and remains constant regardless of further D changes. This transparency distinguishes it from a positive edge-triggered D flip-flop, where Q changes only on the clock’s leading edge.

Step-by-Step Explanation:

Verification / Alternative check:

Timing diagrams show Q mirroring D during the active Enable interval, then flat-lining when the Enable is removed. This is standard behavior in datasheets for transparent latches (e.g., 74HC373/74HC75 families).

Why Other Options Are Wrong:

• (b) The complement follows NOT(D), not D itself; the phrasing is misleading.
• (c) Refers to multi-input devices like S–R or J–K; not relevant here.
• (d) Toggle behavior is for T or J–K flip-flops, not D devices.
• (e) Describes an edge-triggered flip-flop, not a gated latch.

Common Pitfalls:

• Confusing level-sensitive (gated) and edge-triggered behavior.
• Violating setup/hold time around the Enable edge, which can cause metastability.

Final Answer:

The Q output is SET or RESET immediately as the D input goes HIGH or LOW (i.e., Q follows D when enabled).