Question 1

2's complement representation: What decimal number is represented by the binary string 11100101 in 8-bit 2's complement form?

Accepted Answer

Introduction / Context:Two's complement is the standard representation for signed integers in modern digital systems. Interpreting an 8-bit two's complement binary number requires identifying whether it is positive or negative, and then decoding it properly.Given Data / Assumptions:Binary string: 11100101.Word size: 8 bits.Representation: 2's complement.Concept / Approach:In 2's complement, the most significant bit (MSB) is the sign bit. If MSB = 0, the number is positive and interpreted directly. If MSB = 1, the number is negative, and its magnitude is obtained by inverting all bits and adding 1.Step-by-Step Solution:Binary given: 11100101.MSB = 1 ⇒ number is negative.Invert bits: 00011010.Add 1: 00011011 (decimal 27).Therefore, value = −27.Verification / Alternative check:Direct conversion: interpret as unsigned = 229. For 8-bit 2's complement, subtract 256: 229 − 256 = −27. Same result.Why Other Options Are Wrong:+37, +27: positive, contradict MSB = 1.−31: would correspond to binary 11100001.−59: unrelated to this binary string.Common Pitfalls:Forgetting to apply 2's complement inversion +1.Confusing sign-magnitude with 2's complement.Final Answer:-27

Question 2

1's complement operation: What is the 1's complement of the binary number 11100110?

Accepted Answer

Introduction / Context:One's complement is an earlier method of representing signed numbers. It is also a useful digital operation for bit manipulation, where each bit is inverted. This question reinforces knowledge of bitwise inversion.Given Data / Assumptions:Binary input: 11100110.Word length: 8 bits.Concept / Approach:1's complement means flipping every bit: 1→0 and 0→1. This gives the bitwise NOT of the binary number.Step-by-Step Solution:Original: 11100110.Invert each bit: 00011001.Final result: 00011001.Verification / Alternative check:Check bit counts: original has 5 ones, complement has 3 ones. Together, all 8 bits covered.Why Other Options Are Wrong:10000001: only changes some bits, not full complement.00011010: would be the 2's complement of 11100110, not 1's complement.00000000: only if input was 11111111.11111111: only if input was 00000000.Common Pitfalls:Confusing 1's complement with 2's complement (extra +1 step).Final Answer:00011001

Question 3

Combinational circuit design: A full adder circuit can be implemented using which combination of half adders and/or logic gates?

Accepted Answer

Introduction / Context:A full adder is a basic combinational circuit that adds three binary inputs (two significant bits and a carry-in). It is an essential building block for arithmetic logic in CPUs. This question examines how a full adder can be constructed from smaller blocks like half adders.Given Data / Assumptions:Inputs: A, B, and Cin.Outputs: Sum and Cout.Concept / Approach:A half adder adds two bits and produces Sum and Carry. By cascading two half adders and combining carries with an OR gate, we implement a full adder. This construction is standard in digital electronics education.Step-by-Step Solution:First half adder adds A and B: produces Sum1 and Carry1.Second half adder adds Sum1 and Cin: produces final Sum and Carry2.OR gate combines Carry1 and Carry2 to produce Cout.Verification / Alternative check:Boolean expression: Sum = A XOR B XOR Cin; Cout = (A AND B) OR (Cin AND (A XOR B)). Matches the circuit built from two half adders + OR.Why Other Options Are Wrong:'two half adders': missing the OR for carry combination.'NOT gate' addition is irrelevant.'three half adders': unnecessary redundancy.'one half adder and XOR': incomplete for carry-out.Common Pitfalls:Confusing the role of OR vs XOR in carry generation.Final Answer:two half adders and an OR gate

Question 4

In digital electronics, which device has a single data input line and routes that signal to one of many outputs (i.e., one input and many outputs)?

Accepted Answer

Introduction / Context:A core concept in digital systems is signal routing. Two complementary building blocks are the multiplexer (many inputs, one output) and the demultiplexer (one input, many outputs). Knowing which block does what is essential for designing data paths, addressing memory, and distributing clocks or control signals.Given Data / Assumptions:The question asks specifically for a device with one input and many outputs.Standard logic families and definitions are assumed (no exotic custom logic).Concept / Approach:A demultiplexer (DEMUX) accepts a single data input and, based on select lines, connects that input to exactly one of several outputs. By contrast, a multiplexer (MUX) funnels one of many inputs to a single output. Flip-flops and counters are sequential elements, not routing elements; encoders perform the inverse of decoders but still do not match “one input, many outputs”.Step-by-Step Solution:Identify device types: MUX (many-to-one), DEMUX (one-to-many).Match requirement: one input routed to one of many outputs → DEMUX.Eliminate sequential devices (counter, flip-flop) as they do not perform signal distribution.Verification / Alternative check:Textbook truth tables confirm that a 1-to-4 DEMUX has one data input, two select lines, and four outputs; only one output reflects the input at a time.Why Other Options Are Wrong:Multiplexer: many inputs to a single output (opposite direction).Counter: sequential state machine, not a router.Flip-flop: 1-bit storage, not a router.Encoder: many inputs to fewer coded outputs, not one-to-many.Common Pitfalls:Confusing MUX and DEMUX due to their complementary nature; forgetting the role of select lines that steer the single input to a chosen output in a DEMUX.Final Answer:Demultiplexer

Question 5

In an 8-bit two's-complement system, what is the largest-magnitude negative number (i.e., the minimum representable value) that can be stored?

Accepted Answer

Introduction / Context:Two's-complement encoding is the standard for signed integers in digital systems. Understanding its numeric range avoids overflow and sign errors in embedded and computer systems.Given Data / Assumptions:Word size: 8 bits.Signed representation: two's complement.Concept / Approach:For an n-bit two's-complement integer, the value range is from -2^(n-1) to +2^(n-1) - 1. For n = 8, the range is -128 to +127.Step-by-Step Solution:Compute negative limit: -2^(8 - 1) = -2^7 = -128.Compute positive limit: +2^7 - 1 = +127.The “largest negative number” (most negative, minimum) is -128.Verification / Alternative check:Binary 1000 0000 in two's complement equals -128. No other 8-bit pattern is more negative.Why Other Options Are Wrong:-256 and -255: not representable in 8 bits two's complement.-127: not the most negative; it is closer to zero than -128.0: not negative.Common Pitfalls:Interpreting “greatest negative” as closest to zero (e.g., -1); in range questions, it means the minimum value (most negative), which is -128 for 8-bit two's complement.Final Answer:- 128

Question 6

For three variables A, B, C, write the canonical Sum-of-Minterms for Y = Σ m (1, 3, 5, 7). Which expression is correct?

Accepted Answer

Introduction / Context:Canonical forms (Sum-of-Minterms and Product-of-Maxterms) are foundational in logic design, enabling systematic simplification and implementation using standard gates.Given Data / Assumptions:Minterms: m(1, 3, 5, 7).Variables ordered as A (MSB), B, C (LSB).Concept / Approach:Each minterm index corresponds to the binary pattern of ABC. Index → bits: 1 → 001, 3 → 011, 5 → 101, 7 → 111. A 0 bit means complemented variable, a 1 bit means uncomplemented.Step-by-Step Solution:m1 (001) → A'B'Cm3 (011) → A'BCm5 (101) → AB'Cm7 (111) → ABCSum them: Y = A'B'C + A'BC + AB'C + ABCVerification / Alternative check:Create a 3-variable truth table for indices 1,3,5,7 and confirm outputs are 1 only at those rows. K-map grouping also matches this canonical SOP.Why Other Options Are Wrong:Options with any term having a wrong complemented/uncomplemented variable do not match the specified minterm index.Expressions including C' for indices whose LSB is 1 are invalid for this set.Common Pitfalls:Misordering variables (e.g., using C as MSB) and mixing up complements when translating index to literals.Final Answer:Y = A'B'C + A'BC + AB'C + ABC

Question 7

A 5-stage ring counter (one-hot) is built using 5 flip-flops connected in a ring. How many unique states does it cycle through?

Accepted Answer

Introduction / Context:Ring counters are widely used for sequence generation, time-slot selection, and simple state machines in digital systems. They are “one-hot” by design.Given Data / Assumptions:5 flip-flops wired as a ring (one-hot configuration).Exactly one flip-flop is high at any time; the “1” circulates.Concept / Approach:In a ring counter, the number of stable, recurring states equals the number of flip-flops, provided proper initialization to a one-hot state.Step-by-Step Solution:Start with 10000, then 01000, 00100, 00010, 00001.After 5 clocks, the pattern repeats. Hence 5 unique states.Verification / Alternative check:Simulate the ring on paper or HDL; the single “1” advances one stage per clock, cycling through five states before repeating.Why Other Options Are Wrong:10 or 32 states: confuse with Johnson counters or general 5-bit counters.Infinite: the sequence is finite and periodic.2^5 - 1: applies to maximal-length LFSRs, not ring counters.Common Pitfalls:Confusing ring counters with Johnson (twisted ring) counters, which have 2N states.Final Answer:5 states

Question 8

An n-bit DAC has a full-scale (reference) of 5 V and a resolution (LSB size) of 5 mV. What is the value of n?

Accepted Answer

Introduction / Context:DAC resolution links the number of bits to the smallest analog step size. Correctly relating LSB size to full-scale range is fundamental in data conversion design.Given Data / Assumptions:Vref (full-scale) = 5 V.Resolution (LSB) = 5 mV = 0.005 V.Assume ideal straight-binary coding.Concept / Approach:Two common definitions exist: LSB = Vref / (2^n) or LSB = Vref / (2^n - 1). For ideal sizing and most quick estimates, LSB ≈ Vref / 2^n suffices. Using this yields a clean integer n.Step-by-Step Solution:Set 0.005 = 5 / 2^n → 2^n = 1000.n = log2(1000) ≈ 9.966 ≈ 10 bits.Using Vref / (2^n - 1): 5 / 0.005 = 1000 ≈ 2^n - 1 → 2^n ≈ 1001 → still n ≈ 10.Verification / Alternative check:A 10-bit DAC has 1024 steps; LSB ≈ 5 / 1024 ≈ 4.88 mV, very close to 5 mV; the stated resolution is consistent with 10 bits.Why Other Options Are Wrong:8, 9 bits: yield LSBs significantly larger than 5 mV.11 bits: LSB would be roughly 2.44 mV, smaller than specified.Common Pitfalls:Confusing Vref/(2^n) and Vref/(2^n - 1); both give n ≈ 10 here, but always check the convention used in the specific DAC's datasheet.Final Answer:10

Question 9

A 2-input AND gate has inputs A and B, plus an active-high inhibit (S). For which input combination is the output logic-1?

Accepted Answer

Introduction / Context:Inhibit inputs are common control features that disable otherwise-valid outputs. Recognizing the polarity of inhibit (active-high vs. active-low) is crucial to correct logic interpretation.Given Data / Assumptions:Gate: AND with inputs A, B.Inhibit S is active-high (S = 1 disables output).Concept / Approach:Base AND requires A = 1 and B = 1. The active-high inhibit S must be 0 for the output to be enabled. Therefore, the only time output is 1 is when A = 1, B = 1, and S = 0.Step-by-Step Solution:AND condition → A * B = 1 requires A = 1 and B = 1.Inhibit condition → S must be 0 to allow output.Combine → A = 1, B = 1, S = 0.Verification / Alternative check:Truth table inspection confirms that any time S = 1, output is forced low, regardless of A and B.Why Other Options Are Wrong:Any option with S = 1 is inhibited.Any option with A = 0 or B = 0 fails AND condition.Common Pitfalls:Confusing inhibit polarity; assuming it behaves like an enable (active-high) when it is in fact active-high inhibit.Final Answer:A = 1, B = 1, S = 0

Question 10

In digital logic, what are the outputs produced by a half-adder circuit?

Accepted Answer

Introduction / Context:The half-adder is the fundamental combinational block for binary addition. It adds two single-bit operands and produces two outputs representing the result in binary form.Given Data / Assumptions:Inputs: single-bit A and B.No carry-in (that's why it is called “half”-adder).Concept / Approach:The half-adder implements SUM = A ⊕ B and CARRY = A * B. Both outputs are required to represent the full addition result (sum bit and carry-out to the next stage).Step-by-Step Solution:Truth table confirms: (A,B) = (0,0) → SUM=0, CARRY=0; (0,1) → 1,0; (1,0) → 1,0; (1,1) → 0,1.Hence outputs are SUM and CARRY.Verification / Alternative check:Compare with full-adder, which adds A, B, and Cin. A half-adder is the special case with Cin = 0.Why Other Options Are Wrong:Only SUM or only CARRY is incomplete.DIFFERENCE and BORROW: that is a half-subtractor's outputs, not a half-adder's.Common Pitfalls:Confusing adder and subtractor outputs; forgetting that carry arises only when both inputs are 1.Final Answer:SUM and CARRY

Question 11

A ripple counter is built from JK flip-flops with propagation delay t_pd = 12 ns, and is clocked at 10 MHz. What is the largest modulus (2^N) that can safely operate at this frequency?

Accepted Answer

Introduction / Context:Ripple counters cascade flip-flops so that the total propagation delay accumulates along the chain. The maximum clock frequency is constrained by the total worst-case delay through N stages.Given Data / Assumptions:Flip-flop propagation delay t_pd = 12 ns.Clock frequency f_clk = 10 MHz → period T = 100 ns.Asynchronous (ripple) counter; worst-case path spans N stages.Concept / Approach:A common design rule for ripple counters is f_max ≈ 1 / (N * t_pd). The total delay must be less than the clock period to avoid incorrect counting.Step-by-Step Solution:Compute N_max from 1 / (N * 12 ns) ≥ 10 MHz → N ≤ 1 / (10e6 * 12e-9) = 8.33.Thus N_max = 8 stages.Largest modulus = 2^8 = 256.Verification / Alternative check:Timing simulation or STA (static timing analysis) will confirm that with N = 8, cumulative delay ≈ 96 ns, which fits within T = 100 ns margin.Why Other Options Are Wrong:16, 64, 128: smaller moduli than necessary; not the largest possible.512: would require 9 stages → 9 * 12 ns = 108 ns > 100 ns, violating timing.Common Pitfalls:Using synchronous-counter timing limits (which are different); forgetting that ripple counters accumulate delays stage by stage.Final Answer:256

Question 12

For three variables A, B, C, which maxterm index corresponds to the expression A + B + C in canonical Product-of-Maxterms form?

Accepted Answer

Introduction / Context:Canonical Product-of-Maxterms (ΠM) expresses a logic function as the product (AND) of maxterms. Each maxterm corresponds to a specific input combination where the function is zero.Given Data / Assumptions:Variables ordered as A (MSB), B, C (LSB).Maxterm notation Mi corresponds to the input combination i for which the maxterm evaluates to 0 and the function can be zero.Concept / Approach:Maxterm Mi is formed by ORing each variable in true or complemented form such that the term evaluates to 0 for the i-th input combination. For i = 0 → (A, B, C) = (0, 0, 0), the maxterm is A + B + C.Step-by-Step Solution:At input (0,0,0), to force the OR to 0, each literal must be 0 → use A, B, C uncomplemented.Thus the canonical maxterm is A + B + C, which by definition is M0.Verification / Alternative check:Enumerate the 3-variable maxterms: M0 = A + B + C, M1 = A + B + C', etc. Standard tables confirm this mapping.Why Other Options Are Wrong:M1, M3, M4: correspond to different input indices and therefore different literal complements.M7: corresponds to (1,1,1) and is A' + B' + C'.Common Pitfalls:Confusing minterms with maxterms, or mixing up literal complementation rules between SOP and POS canonical forms.Final Answer:M0

Question 13

Boolean algebra practice: For the Boolean expression A + B·C (with variables A, B, C), how many distinct minterms (input combinations) satisfy the expression?

Accepted Answer

Introduction / Context:This digital logic question checks your understanding of minterms and coverage in a three-variable Boolean expression. Knowing how to count satisfying input combinations (minterms) is foundational for Karnaugh maps, simplification, and logic synthesis.Given Data / Assumptions:Expression: A + BC where A, B, C are Boolean variables.Domain: All 2^3 = 8 possible input combinations for (A, B, C).Operator precedence: '·' means AND, '+' means OR.Concept / Approach:A term A in an OR expression A + X covers all cases where A = 1 (regardless of B, C). The product BC contributes additional cases when A = 0 and both B and C are 1. We must avoid double counting overlaps.Step-by-Step Solution:Count cases with A = 1: there are 2^2 = 4 minterms (for all combinations of B, C).Now consider A = 0. Then the expression reduces to BC. Only (B, C) = (1, 1) satisfies BC = 1, which adds exactly 1 new minterm.Total minterms = 4 (from A = 1) + 1 (from A = 0 and BC = 1) = 5.Verification / Alternative check:List explicitly: A = 1 with (B, C) ∈ {(0,0), (0,1), (1,0), (1,1)} → 4 minterms. Plus A = 0, B = 1, C = 1 → 1 minterm. No other A = 0 case works. Sum = 5.Why Other Options Are Wrong:2 or 3: undercount by ignoring A = 1 coverage or the extra BC case at A = 0.4: counts only A = 1 cases and misses the BC case at A = 0.6: overcounts (there is only one additional case when A = 0).Common Pitfalls:Double counting the case A = 1, B = 1, C = 1 (already counted in A = 1 set).Forgetting that BC only matters when A = 0.Final Answer:5

Question 14

Computer arithmetic design: Why is a carry look-ahead adder commonly preferred for binary addition in high-speed digital systems?

Accepted Answer

Introduction / Context:Adders are central to arithmetic logic units (ALUs). Ripple-carry adders are simple but slow because each bit's carry must wait for the previous one. Carry look-ahead adders (CLAs) improve speed by computing carries in parallel using generate/propagate logic.Given Data / Assumptions:Comparing ripple-carry vs. carry look-ahead techniques.Metric of interest: addition speed (latency).Accuracy of addition is identical for correct implementations.Concept / Approach:CLA forms carry generate (Gi = AiBi) and carry propagate (Pi = Ai + Bi) signals to compute all carries through combinational look-ahead networks. This removes the linear dependency of carry propagation and reduces critical path delay.Step-by-Step Solution:Define Gi = AiBi and Pi = Ai + Bi for every bit i.Compute carries: C1 = G0 + P0C0; C2 = G1 + P1G0 + P1P0C0; and so on.Because carries are produced in parallel (via logic trees), total delay scales logarithmically or by block rather than linearly with word length.Verification / Alternative check:In timing analysis, a CLA's worst-case delay is substantially less than an n-bit ripple adder (which is O(n)). Thus, CLAs are the industry standard for high-speed addition.Why Other Options Are Wrong:Cost / gate count: CLAs typically use more gates and wiring than ripple-carry.Accuracy: Not a differentiator—both produce correct sums.'Needs no propagation delay': impossible in real circuits.Common Pitfalls:Assuming fewer gates always means faster; interconnect and carry logic dominate speed.Final Answer:It is faster

Question 15

Counters and decade operation: A BCD (decade) counter counts 0–9 and then resets. Which binary state range does it skip during counting?

Accepted Answer

Introduction / Context:Decade (BCD) counters represent decimal digits (0 through 9) in binary-coded decimal. After reaching 1001 (decimal 9), they reset to 0000 and do not pass through states representing 10–15 in pure binary. Recognizing the skipped range is essential in counter design and state-diagram logic.Given Data / Assumptions:Counter outputs are four-bit binary codes.Valid outputs: 0000 (0) to 1001 (9).Invalid / skipped outputs: binary 10 to 15.Concept / Approach:Binary states from 1010 to 1111 correspond to decimal 10 through 15. In BCD counting, these states are inhibited or quickly forced back to 0000 via synchronous or asynchronous reset logic.Step-by-Step Solution:List states: 0000 (0) … 1001 (9) are valid.Next binary state 1010 (10) is not allowed; counter resets to 0000.Therefore, the counter skips 1010, 1011, 1100, 1101, 1110, 1111.Verification / Alternative check:BCD truth tables and 74xx decade counter datasheets (e.g., 7490/7493 derived designs with gating) confirm reset at 10.Why Other Options Are Wrong:1000–1111: includes valid 8 and 9.0000–0011: valid for 0–3.'1111 to higher': imprecise; not a contiguous skipped band in BCD.Common Pitfalls:Confusing BCD counters with pure modulo-16 binary counters.Final Answer:binary states 1010 to 1111

Question 16

Minimum number of 2-input NAND gates required to implement the function F = (x + y) (Z + W) is

Accepted Answer

F = (x + y) (z + w) = xy.(z + w) = xyz + xyw = minimum no. of 2 input NAND gate.

Question 17

Core memory element in digital electronics: Which component is the fundamental storage element used to store a single bit?

Accepted Answer

Introduction / Context:At the heart of sequential logic is a circuit that can store one bit of information reliably. Understanding which component provides this function is critical for designing registers, state machines, and memory structures.Given Data / Assumptions:Single-bit storage is required.Options include common combinational and sequential building blocks.Concept / Approach:A flip-flop (e.g., SR, JK, D, T) is a bistable sequential element with two stable states, capable of latching a single bit. Other components like multiplexers, encoders, and decoders process data but do not inherently store state without additional feedback.Step-by-Step Solution:Flip-flop provides two stable states (logic 0 and 1) with clocked or level-sensitive control.Counters are cascaded flip-flops; they store multiple bits, but the fundamental element inside is still a flip-flop.Multiplexers, encoders, decoders are combinational and do not store state.Verification / Alternative check:Check any register design: it is a bank of D flip-flops, each storing one bit and controlled by a clock and enable/reset as needed.Why Other Options Are Wrong:Counter: stores multiple bits but is built from flip-flops; not the atomic storage element.Multiplexer/encoder/decoder: routing/encoding functions only.Common Pitfalls:Confusing a multi-bit structure (counter) with the base single-bit storage element (flip-flop).Final Answer:flip flop

Question 18

Counter-type ADC timing: A counter-type A/D converter uses a 4-bit counter with a 2 MHz clock. What is the worst-case conversion time?

Accepted Answer

Introduction / Context:Counter (ramp) type ADCs perform conversion by counting clock pulses until the DAC output matches or exceeds the analog input. The worst-case time occurs when the input is near full scale and the counter must traverse almost all codes.Given Data / Assumptions:Resolution: 4 bits ⇒ 2^4 = 16 codes.Clock frequency: 2 MHz (period = 0.5 μs).Worst case approximates one full count range (up to 16 cycles for reach/compare).Concept / Approach:Worst-case conversion time T_wc ≈ (2^n) / f_clk for an n-bit counter-type ADC. Some treatments use (2^n − 1), but with comparator/DAC settling, the nominal worst-case closely tracks 2^n counts.Step-by-Step Solution:n = 4 ⇒ 2^n = 16 counts.Clock period = 1 / 2 MHz = 0.5 μs.T_wc ≈ 16 * 0.5 μs = 8 μs.Verification / Alternative check:Using (2^n − 1) * T_clk = 15 * 0.5 μs = 7.5 μs; with practical settling and control overhead, 8 μs is the accepted figure among given options.Why Other Options Are Wrong:10 μs: would imply fewer counts per μs than available.2 μs or 5 μs: underestimate required counts.Common Pitfalls:Confusing average conversion time (~ half worst case) with worst case.Final Answer:8 μs

Question 19

Radix conversions: Convert the decimal number 43 to (i) hexadecimal and (ii) Binary-Coded Decimal (BCD).

Accepted Answer

Introduction / Context:Base conversion is a routine but crucial skill in digital systems. Hexadecimal offers compact binary representation, while BCD encodes each decimal digit into a 4-bit nibble, commonly used for displays and decimal arithmetic interfaces.Given Data / Assumptions:Decimal number: 43.Hexadecimal conversion required.BCD encoding required (4 bits per decimal digit).Concept / Approach:For hex: repeatedly divide by 16 or decompose into high and low nibbles. For BCD: encode each decimal digit individually (4 → 0100, 3 → 0011).Step-by-Step Solution:Hex: 43 / 16 = 2 remainder 11 (B). So 43₁₀ = 2B₁₆.BCD: '4' → 0100, '3' → 0011, so BCD(43) = 0100 0011.Verification / Alternative check:Binary of 43 is 0010 1011; grouping nibbles gives 0x2B. BCD is per digit; concatenation yields 0100 0011 as expected.Why Other Options Are Wrong:B2: would correspond to 178 decimal, not 43.00110100 is BCD for 34, not 43.01000100 corresponds to the digits 4 and 4, not 4 and 3.Common Pitfalls:Confusing BCD with straight binary; BCD encodes digits, not the entire number's binary form.Final Answer:2B, 01000011

Question 20

Binary fundamentals: What is the 4-bit binary representation of decimal number 10?

Accepted Answer

Introduction / Context:Decimal-to-binary conversion underpins all digital design, from addressing to arithmetic. Quick mental conversion is invaluable for debugging and hardware design.Given Data / Assumptions:Decimal value: 10.Target width: 4 bits (sufficient because 10 Concept / Approach:Express 10 as a sum of powers of two: 8 + 2. Set the bits corresponding to 8 (2^3) and 2 (2^1).Step-by-Step Solution:2^3 = 8 → bit pattern 1xxx.2^1 = 2 → add 0010.Combine: 1000 + 0010 = 1010.Verification / Alternative check:1010₂ = (18) + (04) + (12) + (01) = 10₁₀.Why Other Options Are Wrong:1110 = 14, 1001 = 9, 1000 = 8, 0110 = 6.Common Pitfalls:Swapping bit order; remember MSB corresponds to highest power of two.Final Answer:1010

Digital Electronics Questions

Questions

Practice smarter