Counter-type ADC timing: A counter-type A/D converter uses a 4-bit counter with a 2 MHz clock. What is the worst-case conversion time?

Introduction / Context:
Counter (ramp) type ADCs perform conversion by counting clock pulses until the DAC output matches or exceeds the analog input. The worst-case time occurs when the input is near full scale and the counter must traverse almost all codes.

Given Data / Assumptions:

• Resolution: 4 bits ⇒ 2^4 = 16 codes.
• Clock frequency: 2 MHz (period = 0.5 μs).
• Worst case approximates one full count range (up to 16 cycles for reach/compare).

Concept / Approach:
Worst-case conversion time T_wc ≈ (2^n) / f_clk for an n-bit counter-type ADC. Some treatments use (2^n − 1), but with comparator/DAC settling, the nominal worst-case closely tracks 2^n counts.

Step-by-Step Solution:

Verification / Alternative check:
Using (2^n − 1) * T_clk = 15 * 0.5 μs = 7.5 μs; with practical settling and control overhead, 8 μs is the accepted figure among given options.

Why Other Options Are Wrong:

Common Pitfalls:

Final Answer: