DRAM control signal convention During a DRAM read cycle, what is the correct logic level of the Read/Write (R/W or WE) control signal?

Introduction / Context:Dynamic RAMs (DRAMs) use control pins such as RAS, CAS, and a write-control pin (often labeled WE or R/W). Knowing the correct polarity of these signals for read versus write is essential when designing memory controllers or debugging bus transactions.

Given Data / Assumptions:

• Typical DRAM write-enable pin (WE) is active-LOW for write.
• Read occurs when WE is deasserted (logic HIGH) while RAS/CAS perform row/column latching.
• Exact naming varies, but the polarity convention is consistent: LOW = write, HIGH = read.

Concept / Approach:

If the write-control input is LOW, the device performs a write when properly addressed. To read, the write function must be disabled, which is achieved by setting WE (or R/W) HIGH so the sense amps drive data out during the CAS phase.

Step-by-Step Solution:

Verification / Alternative check:

Cross-check with standard DRAM timing diagrams: WE = 1 for read, WE = 0 for write, with RAS/CAS sequencing the row and column.

Why Other Options Are Wrong:

• Low: would initiate write.
• Hi-Z: control inputs are driven logic signals, not tri-stated.
• None of the above: unnecessary since HIGH is correct.

Common Pitfalls:

• Confusing signal labels (R/W vs WE). Always check active polarity in the datasheet; conventionally, read requires WE HIGH.

Final Answer:

High