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Home ‣ Digital Electronics ‣ Flip-Flops Comments
  • Question

  • A positive edge-triggered flip-flop will accept inputs only when the clock ________.


  • Options
  • A. is LOW
  • B. changes from HIGH to LOW
  • C. is HIGH
  • D. changes from LOW to HIGH

  • Correct Answer
  • changes from LOW to HIGH 

    • Flip-Flops problems

    Search Results

    • 1. A gated D latch does not have ________.

    • Options
    • A. a clock input
    • B. an enable input
    • C. a output
    • D. steering gates
      • Discuss
    • 2. The signal used to identify edge-triggered flip-flops is ________.

    • Options
    • A. a bubble on the clock input
    • B. an inverted "L" on the output
    • C. the letter "E" on the enable input
    • D. a triangle on the clock input
      • Discuss
    • 3. A gated S-R flip-flop goes into the CLEAR condition when ________.

    • Options
    • A. S is HIGH; R is LOW; EN is HIGH
    • B. S is LOW; R is HIGH; EN is HIGH
    • C. S is LOW; R is HIGH; EN is LOW
    • D. S is HIGH; R is LOW; EN is LOW
      • Discuss
    • 4. The point(s) on this timing diagram where the Q output of a D latch will be HIGH is/are ________.


    • Options
    • A. point 4
    • B. points 3 and 4
    • C. points 1 and 2
    • D. points 4 and 5
      • Discuss
    • 5. A retriggerable one-shot has a pulse width of 10 ms; 3 ms after being triggered, another trigger pulse is applied. The resulting output pulse will be ________ mS.

    • Options
    • A. 3
    • B. 7
    • C. 10
    • D. 13
      • Discuss
    • 6. A gated S-R flip-flop is in the hold condition whenever ________.

    • Options
    • A. the Gate Enable is HIGH
    • B. the Gate Enable is LOW
    • C. the S and R inputs are both LOW
    • D. the Gate Enable is HIGH and the S and R inputs are both LOW
      • Discuss
    • 7. The postponed symbol () on the output of a flip-flop identifies it as being ________.

    • Options
    • A. a D flip-flop
    • B. a J-K flip-flop
    • C. pulse triggered
    • D. trailing edge-triggered
      • Discuss
    • 8. When the output of the NOR gate S-R flip-flop is in the HOLD state (no change), the inputs are ________.

    • Options
    • A. S = 1, R = 1
    • B. S = 1, R = 0
    • C. S = 0, R = 1
    • D. S = 0, R = 0
      • Discuss
    • 9. The advantage of a J-K flip-flop over an S-R FF is that ________.

    • Options
    • A. it has fewer gates
    • B. it has only one output
    • C. it has no invalid states
    • D. it does not require a clock input
      • Discuss
    • 10. A major drawback to an latch is its ________.

    • Options
    • A. complexity
    • B. slow speed
    • C. invalid condition
    • D. latch mode
      • Discuss

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