logo

CuriousTab

CuriousTab

Discussion

Home ‣ Digital Electronics ‣ Flip-Flops Comments
  • Question

  • The point(s) on this timing diagram where the Q output of a D latch will be HIGH is/are ________.

    The point(s) on this timing diagram where the Q output of a D latch will be HIGH is/are ________. po


  • Options
  • A. point 4
  • B. points 3 and 4
  • C. points 1 and 2
  • D. points 4 and 5

  • Correct Answer
  • point 4 

    • Flip-Flops problems

    Search Results

    • 1. A retriggerable one-shot has a pulse width of 10 ms; 3 ms after being triggered, another trigger pulse is applied. The resulting output pulse will be ________ mS.

    • Options
    • A. 3
    • B. 7
    • C. 10
    • D. 13
      • Discuss
    • 2. What type of multivibrator is a latch?

    • Options
    • A. Astable
    • B. Monostable
    • C. Bistable
    • D. It depends on the type of latch.
      • Discuss
    • 3. The asynchronous inputs are normally labeled ________ and ________, and are normally active-________ inputs.

    • Options
    • A. PRE, CLR, LOW
    • B. ON, OFF, HIGH
    • C. START, STOP, LOW
    • D. SET, RESET, HIGH
      • Discuss
    • 4. When the output of the NOR gate S-R flip-flop is Q = 0 and , the inputs are:

    • Options
    • A. S = 1, R = 1
    • B. S = 1, R = 0
    • C. S = 0, R = 1
    • D. S = 0, R = 0
      • Discuss
    • 5. Regardless of whether you develop a description in AHDL or VHDL, the circuit's proper operation can be verified using a ________.

    • Options
    • A. PROCESS
    • B. computer
    • C. simulator
    • D. primitive library
      • Discuss
    • 6. A gated S-R flip-flop goes into the CLEAR condition when ________.

    • Options
    • A. S is HIGH; R is LOW; EN is HIGH
    • B. S is LOW; R is HIGH; EN is HIGH
    • C. S is LOW; R is HIGH; EN is LOW
    • D. S is HIGH; R is LOW; EN is LOW
      • Discuss
    • 7. The signal used to identify edge-triggered flip-flops is ________.

    • Options
    • A. a bubble on the clock input
    • B. an inverted "L" on the output
    • C. the letter "E" on the enable input
    • D. a triangle on the clock input
      • Discuss
    • 8. A gated D latch does not have ________.

    • Options
    • A. a clock input
    • B. an enable input
    • C. a output
    • D. steering gates
      • Discuss
    • 9. A positive edge-triggered flip-flop will accept inputs only when the clock ________.

    • Options
    • A. is LOW
    • B. changes from HIGH to LOW
    • C. is HIGH
    • D. changes from LOW to HIGH
      • Discuss
    • 10. A gated S-R flip-flop is in the hold condition whenever ________.

    • Options
    • A. the Gate Enable is HIGH
    • B. the Gate Enable is LOW
    • C. the S and R inputs are both LOW
    • D. the Gate Enable is HIGH and the S and R inputs are both LOW
      • Discuss

    Comments

    There are no comments.
Enter a new Comment




Aptitude

Engineering

Programming

Reasoning

Links

Copyright ©CuriousTab. All rights reserved.