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Home ‣ Digital Electronics ‣ Flip-Flops Comments
  • Question

  • Pulse-triggered or level-triggered devices are the same.


  • Options
  • A. True
  • B. False

  • Correct Answer
  • True 

    • Flip-Flops problems

    Search Results

    • 1. A TOGGLE input to a J-K flip-flop causes the Q and outputs to switch to their opposite state.

    • Options
    • A. True
    • B. False
      • Discuss
    • 2. The propagation delay time tPLH is measured from the triggering edge of the clock pulse to the LOW-to-HIGH transition of the output.

    • Options
    • A. True
    • B. False
      • Discuss
    • 3. Edge-triggered J-K flip-flops make it hard for design engineers to know when to accept input data.

    • Options
    • A. True
    • B. False
      • Discuss
    • 4. Pulse-triggered flip-flops are identified by a bubble on the Q output terminal.

    • Options
    • A. True
    • B. False
      • Discuss
    • 5. VHDL does require a special designation for an output with a feedback.

    • Options
    • A. True
    • B. False
      • Discuss
    • 6. A latch can act as a contact-bounce eliminator.

    • Options
    • A. True
    • B. False
      • Discuss
    • 7. A one-shot is a special type of multivibrator that must be triggered to produce each output pulse.

    • Options
    • A. True
    • B. False
      • Discuss
    • 8. When using edge-triggered flip-flops, the data is entered into the flip-flop on the leading edge of the clock, but the output does not change until the trailing edge of the clock.

    • Options
    • A. True
    • B. False
      • Discuss
    • 9. In VHDL, each instance of a component is given a name followed by a semicolon and the name of the library primitive.

    • Options
    • A. True
    • B. False
      • Discuss
    • 10. PRESET and CLEAR inputs are normally synchronous.

    • Options
    • A. True
    • B. False
      • Discuss

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