Curioustab
Aptitude
General Knowledge
Verbal Reasoning
Computer Science
Interview
Aptitude
General Knowledge
Verbal Reasoning
Computer Science
Interview
Home
»
Digital Electronics
»
Flip-Flops
A negative edge-triggered flip-flop will accept inputs only when the clock is LOW.
True
Correct Answer:
False
← Previous Question
Next Question→
More Questions from
Flip-Flops
Latches are tristate devices whose state normally depends on asynchronous inputs.
The term CLEAR always means that .
Parallel data transfers between two different sets of registers require more than one shift pulse.
The J-K flip-flop is a standard building block of clocked (sequential) logic circuits known as logic standard primitives.
A D flip-flop is constructed by connecting an inverter between the SET and clock terminals.
A flip-flop is in the CLEAR condition when .
The J-K flip-flop eliminates the invalid state by toggling when both inputs are high and the clock transitions.
A D latch has one data-input line.
The 7474 has two distinct types of inputs: synchronous and asynchronous.
The gated S-R flip-flop is asynchronous.
Discussion & Comments
No comments yet. Be the first to comment!
Name:
Comment:
Post Comment
Join Discussion
Discussion & Comments