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  • Question
  • Which segments of a seven-segment display would be required to be active to display the decimal digit 2?


  • Options
  • A. a, b, d, e, and g
  • B. a, b, c, d, and g
  • C. a, c, d, f, and g
  • D. a, b, c, d, e, and f

  • Correct Answer
  • a, b, d, e, and g 


  • Counters problems


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    • 1. A MOD-16 synchronous counter has inputs labeled . These inputs would most probably be used to:

    • Options
    • A. reset the counter to 0000 at the end of each count cycle
    • B. preset the counter to a value determined by the inputs any time the is active-HIGH
    • C. preset the counter to a value determined by the inputs any time the is active-LOW
    • D. reset the counter to 0000 any time is active-HIGH and is active-LOW
    • Discuss
    • 2. How many flip-flops are required to make a MOD-32 binary counter?

    • Options
    • A. 3
    • B. 45
    • C. 5
    • D. 6
    • Discuss
    • 3. The designation means that the ________.

    • Options
    • A. up count is active-HIGH, the down count is active-LOW
    • B. up count is active-LOW, the down count is active-HIGH
    • C. up and down counts are both active-LOW
    • D. up and down counts are both active-HIGH
    • Discuss
    • 4. What function does the CTR DIV 8 circuit given below perform?


    • Options
    • A. It divides the clock frequency down to match the frequency of the serial data in.
    • B. The divide-by-8 counter is triggered by the control flip-flop and clock, which then allows the data output register to begin storing the input data. Once all eight data bits are stored in the data output register, the data output register and the divide-by-8 counter trigger the one-shot. The one-shot then begins the process all over again.
    • C. The divide-by-8 counter is used to verify that the parity bit is attached to the input data string.
    • D. It keeps track of the eight data bits, triggering the transfer of the data through the output register and the one-shot, which then resets the control flip-flop and divide-by-8 counter.
    • Discuss
    • 5. Three cascaded modulus-5 counters have an overall modulus of ________.

    • Options
    • A. 5
    • B. 25
    • C. 125
    • D. 500
    • Discuss
    • 6. Which of the following groups of logic devices would be the minimum required for a MOD-64 synchronous counter?

    • Options
    • A. Five flip-flops, three AND gates
    • B. Seven flip-flops, five AND gates
    • C. Four flip-flops, ten AND gates
    • D. Six flip-flops, four AND gates
    • Discuss
    • 7. A multiplexed display being driven by a logic circuit:

    • Options
    • A. accepts data inputs from one line and passes this data to multiple output lines
    • B. accepts data inputs from several lines and allows one of them at a time to pass to the output
    • C. accepts data inputs from multiple lines and passes this data to multiple output lines
    • D. accepts data inputs from several lines and multiplexes this input data to four BCD lines
    • Discuss
    • 8. A 12 MHz clock frequency is applied to a cascaded counter containing a modulus-5 counter, a modulus-8 counter, and a modulus-10 counter. The lowest output frequency possible is ________.

    • Options
    • A. 10 kHz
    • B. 20 kHz
    • C. 30 kHz
    • D. 60 kHz
    • Discuss
    • 9. What is meant by parallel load of a counter?

    • Options
    • A. Each FF is loaded with data on a separate clock.
    • B. The counter is cleared.
    • C. All FFs are preset with data.
    • Discuss
    • 10. A 4-bit up/down binary counter is in the DOWN mode and in the 1100 state. To what state does the counter go on the next clock pulse?

    • Options
    • A. 1101
    • B. 1011
    • C. 1111
    • D. 0000
    • Discuss


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